messages from 2025-10-29 22:39:56 to 2025-10-31 18:10:45 UTC [more...]
[PULL] drm-misc-fixes
2025-10-31 18:10 UTC (2+ messages)
[PULL] drm-intel-fixes
2025-10-31 18:09 UTC (2+ messages)
[PATCH v2] drm/display/dp: Rename bit 4 of DPCD TEST_REQUEST to match DP2.1 spec
2025-10-31 17:57 UTC
[PULL] drm-misc-next
2025-10-31 17:53 UTC (2+ messages)
[PULL] drm-xe-next
2025-10-31 17:46 UTC (2+ messages)
[PATCH v2 00/32] drm/i915/display: Add initial support for Xe3p_LPD
2025-10-31 17:36 UTC (20+ messages)
` [PATCH v2 11/32] drm/i915/xe3p_lpd: Underrun debuggability and error codes/hints
` [PATCH v2 13/32] drm/i915/xe3p_lpd: Adapt to updates on MBUS_CTL/DBUF_CTL registers
` [PATCH v2 14/32] drm/i915/wm: Reorder adjust_wm_latency() for Xe3_LPD
` [PATCH v2 15/32] drm/i915/xe3p_lpd: Always apply level-0 watermark adjustment
` [PATCH v2 19/32] drm/i915/xe3p_lpd: PSR SU minimum lines is 4
[PATCH] drm/i915/rom: convert intel_rom interfaces to struct drm_device
2025-10-31 16:53 UTC (2+ messages)
` ✗ Fi.CI.BUILD: failure for drm/i915/rom: convert intel_rom interfaces to struct drm_device (rev2)
[PATCH] drm/i915/dmabuf: Flush the cache in vmap
2025-10-31 16:50 UTC (12+ messages)
[CI 00/32] [PATCH 00/32] drm/i915/display: Add MTL+ platforms to support dpll framework
2025-10-31 15:03 UTC (34+ messages)
` [CI 01/32] drm/i915/display: Rename TBT functions to be ICL specific
` [CI 02/32] drm/i915/display: Factor out C10 msgbus access start/end helpers
` [CI 03/32] drm/i915/display: Sanitize setting the Cx0 PLL use_c10 flag
` [CI 04/32] drm/i915/display: Sanitize calculating C20 PLL state from tables
` [CI 05/32] drm/i915/display: Track the C20 PHY VDR state in the PLL state
` [CI 06/32] drm/i915/display: Move definition of Cx0 PHY functions earlier
` [CI 07/32] drm/i915/display: Add macro to get DDI port width from a register value
` [CI 08/32] drm/i915/display: Track the Cx0 PHY enabled lane count in the PLL state
` [CI 09/32] drm/i915/display: Sanitize C10 PHY PLL SSC register setup
` [CI 10/32] drm/i915/display: Read out the Cx0 PHY SSC enabled state
` [CI 11/32] drm/i915/display: Determine Cx0 PLL DP mode from PLL state
` [CI 12/32] drm/i915/display: Determine Cx0 PLL port clock "
` [CI 13/32] drm/i915/display: Zero Cx0 PLL state before compute and HW readout
` [CI 14/32] drm/i915/display: Print additional Cx0 PLL HW state
` [CI 15/32] drm/i915/display: Remove state verification
` [CI 16/32] drm/i915/display: PLL information for MTL+
` [CI 17/32] drm/i915/display: Update C10/C20 state calculation
` [CI 18/32] drm/i915/display: Compute plls for MTL+ platform
` [CI 19/32] drm/i915/display: MTL+ .get_dplls
` [CI 20/32] drm/i915/display: MTL+ .put_dplls
` [CI 21/32] drm/i915/display: Add .update_active_dpll
` [CI 22/32] drm/i915/display: Add .update_dpll_ref_clks
` [CI 23/32] drm/i915/display: Add .dump_hw_state
` [CI 24/32] drm/i915/display: Add .compare_hw_state
` [CI 25/32] drm/i915/display: Add .get_hw_state to MTL+ platforms
` [CI 26/32] drm/i915/display: Add .get_freq "
` [CI 27/32] drm/i915/display: Add .crtc_get_dpll hook
` [CI 28/32] drm/i915/display: PLL verify debug state print
` [CI 29/32] drm/i915/display: Add .enable_clock on DDI for MTL+ platforms
` [CI 30/32] drm/i915/display: Get configuration for C10 and C20
` [CI 31/32] drm/i915/display: Add Thunderbolt support
` [CI 32/32] drm/i915/display: Enable dpll framework for MTL+
` ✓ i915.CI.BAT: success for drm/i915/display: Add MTL+ platforms to support dpll framework (rev2)
[PATCH] drm/i915/gem: Fix NULL pointer dereference in eb_release_vmas()
2025-10-31 15:03 UTC (5+ messages)
` ✓ i915.CI.BAT: success for "
[PATCH 0/3] drm/displayid: quirk incorrect DisplayID checksums
2025-10-31 13:48 UTC (4+ messages)
` [PATCH 3/3] drm/displayid: add quirk to ignore DisplayID checksum errors
` ✓ i915.CI.BAT: success for drm/displayid: quirk incorrect DisplayID checksums (rev2)
[PATCH v3 00/25] Enable LT PHY
2025-10-31 13:35 UTC (28+ messages)
` [PATCH v3 01/25] drm/i915/ltphy: Add LT Phy related VDR and Pipe Registers
` [PATCH v3 02/25] drm/i915/cx0: Change register bit naming for powerdown values
` [PATCH v3 03/25] drm/i915/ltphy: Phy lane reset for LT Phy
` [PATCH v3 04/25] drm/i915/cx0: Move the HDMI FRL function to intel_hdmi
` [PATCH v3 05/25] drm/i915/ltphy: Program sequence for PORT_CLOCK_CTL for LT Phy
` [PATCH v3 06/25] drm/i915/ltphy: Add a wrapper for LT Phy powerdown change sequence
` [PATCH v3 07/25] drm/i915/ltphy: Read PHY_VDR_0_CONFIG register
` [PATCH v3 08/25] drm/i915/ltphy: Add LT Phy Programming recipe tables
` [PATCH v3 09/25] drm/i915/ltphy: Program the VDR PLL registers for LT PHY
` [PATCH v3 10/25] drm/i915/ltphy: Update the ltpll config table value for eDP
` [PATCH v3 11/25] drm/i915/ltphy: Enable SSC during port clock programming
` [PATCH v3 12/25] drm/i915/ltphy: Add function to calculate LT PHY port clock
` [PATCH v3 13/25] drm/i915/ltphy: Program the P2P Transaction flow for LT Phy
` [PATCH v3 14/25] drm/i915/ltphy: Program the rest of the PORT_CLOCK_CTL steps
` [PATCH v3 15/25] drm/i915/ltphy: Program the rest of the LT Phy Enable sequence
` [PATCH v3 16/25] drm/i915/ltphy: Program LT Phy Non-TBT PLL disable sequence
` [PATCH v3 17/25] drm/i915/ltphy: Hook up LT Phy Enable & Disable sequences
` [PATCH v3 18/25] drm/i915/ddi: Define LT Phy Swing tables
` [PATCH v3 19/25] drm/i915/ltphy: Program LT Phy Voltage Swing
` [PATCH v3 20/25] drm/i915/ltphy: Enable/Disable Tx after Non TBT Enable sequence
` [PATCH v3 21/25] drm/i915/ltphy: Define the LT Phy state compare function
` [PATCH v3 22/25] drm/i915/ltphy: Define function to readout LT Phy PLL state
` [PATCH v3 23/25] drm/i915/ltphy: Define LT PHY PLL state verify function
` [PATCH v3 24/25] drm/i915/display: Aux Enable and Display powerwell timeouts
` [PATCH v3 25/25] drm/i915/ltphy: Modify the step that need to be skipped
` ✗ Fi.CI.BUILD: failure for Enable LT PHY (rev3)
[PATCH v3 0/6] Use display parent interface for runtime pm
2025-10-31 12:29 UTC (11+ messages)
` [PATCH v3 1/6] drm/{i915, xe}/display: pass parent interface to display probe
` [PATCH v3 2/6] drm/{i915, xe}/display: Add display runtime pm parent interface
` [PATCH v3 3/6] drm/i915/display: Runtime pm wrappers for display "
` [PATCH v3 4/6] drm/xe/display: "
` [PATCH v3 5/6] drm/i915/display: Use display parent interface for i915 runtime pm
` [PATCH v3 6/6] drm/xe/display: Use display parent interface for xe "
` ✓ i915.CI.BAT: success for Use display parent interface for runtime pm (rev3)
` ✗ i915.CI.Full: failure "
[PATCH 0/3] drm/1915/dram: Fix DIMM_S decoding on ICL
2025-10-31 11:53 UTC (3+ messages)
` ✓ i915.CI.BAT: success for "
` ✓ i915.CI.Full: "
[PATCH v2 0/4] drm/i915/x3p_lpd: FBC related patches
2025-10-31 11:37 UTC (10+ messages)
` [PATCH v2 1/4] drm/i915/xe3p_lpd: Extend FBC support to UINT16 formats
` [PATCH v2 2/4] drm/i915/xe3p_lpd: Add FBC support for FP16 formats
` [PATCH v2 3/4] drm/i915/xe3p_lpd: extract pixel format valid routine "
` [PATCH v2 4/4] drm/i915/xe3p_lpd: use pixel normalizer for fp16 formats for FBC
[PATCH 0/6] drm/i915: i915_utils.h refactoring
2025-10-31 11:26 UTC (18+ messages)
` [PATCH 1/6] drm/i915: split out separate files for jiffies timeout and wait helpers
` [PATCH 2/6] drm/i915/display: create intel_display_utils.h
` [PATCH 3/6] drm/i915/display: add intel_display_run_as_guest()
` [PATCH 4/6] drm/i915/display: add intel_display_vtd_active()
` [PATCH 5/6] drm/i915/display: switch to intel_display_utils.h
` [PATCH 6/6] drm/xe/compat: reduce i915_utils.[ch]
[PATCH v2 1/2] drm/i915/dsi: log send packet sequence errors
2025-10-31 11:06 UTC (3+ messages)
[PATCH v3 0/4] drm: replace drm_print.h includes from headers with a forward declaration
2025-10-31 10:01 UTC (4+ messages)
[PATCH] drm/i915/gt: Use standard API for seqcount read in TLB invalidation
2025-10-31 9:59 UTC (3+ messages)
[PATCH v3 0/3] drm/i915: Avoid lock inversion when pinning to GGTT
2025-10-31 9:55 UTC (2+ messages)
[PATCH] drm/display/dp: Rename bit 4 of DPCD TEST_REQUEST to match DP2.1 spec
2025-10-31 9:35 UTC (7+ messages)
[PATCH] drm/i915: Fix conversion between clock ticks and nanoseconds
2025-10-31 8:40 UTC (4+ messages)
[PATCH v2 00/26] Enable LT PHY
2025-10-31 6:24 UTC (5+ messages)
` [PATCH v2 12/26] drm/i915/ltphy: Add function to calculate LT PHY port clock
` [PATCH v2 26/26] drm/i915/ltphy: Implement HDMI Algo for Pll state
[PULL] drm-xe-fixes
2025-10-30 20:44 UTC
[PATCH 0/9] PCI: BAR resizing fix/rework
2025-10-30 14:37 UTC (4+ messages)
` [PATCH 6/9] drm/xe: Remove driver side BAR release before resize
[PATCH v1] Support Intel Xe GPU dirver Porting on RISC-V Architecture
2025-10-30 13:34 UTC (6+ messages)
[PATCH] dma-buf: Take a breath during dma-fence-chain subtests
2025-10-30 13:32 UTC (11+ messages)
[PATCH 0/5] Fix Adaptive Sync SDP for Panel Replay
2025-10-30 13:15 UTC (12+ messages)
` [PATCH 1/5] drm/i915/dp: Fix readback for target_rr in Adaptive Sync SDP
` [PATCH 2/5] drm/i915/dp: Allow AS_SDP only if panel replay + auxless alpm is supported
` [PATCH 3/5] drm/i915/display: Take into account AS SDP in intel_dp_sdp_min_guardband
` [PATCH 4/5] drm/i915/alpm: Compute LOBF late after guardband is already determined
` [PATCH 5/5] drm/i915/alpm: Allow LOBF only if window1 > alpm check_entry lines
[PATCH v2] drm/i915/display: Take into account AS SDP in intel_dp_sdp_min_guardband
2025-10-30 13:08 UTC (3+ messages)
[PATCH] drm/i915: remove redundant __GFP_NOWARN
2025-10-29 4:11 UTC
[PATCH 02/22] vfio/hisi: Convert to the get_region_info op
2025-10-28 1:55 UTC (2+ messages)
[PATCH 0/6] Fix Adaptive Sync SDP for Panel Replay
2025-10-30 9:28 UTC (7+ messages)
` [PATCH 1/6] drm/i915/dp: Fix readback for target_rr in Adaptive Sync SDP
` [PATCH 2/6] drm/i915/vrr: Avoid vrr for PCON with HDMI2.1 sink
` [PATCH 3/6] drm/i915/dp: Allow AS_SDP only if panel replay + auxless alpm is supported
` [PATCH 4/6] drm/i915/display: Take into account AS SDP in intel_dp_sdp_min_guardband
` [PATCH 5/6] drm/i915/alpm: Compute LOBF late after guardband is already determined
` [PATCH 6/6] drm/i915/alpm: Allow LOBF only if window1 > alpm check_entry lines
[PATCH 1/9] PCI: Prevent resource tree corruption when BAR resize fails
2025-10-30 8:22 UTC (3+ messages)
linux-next: manual merge of the backlight tree with the drm-misc tree
2025-10-30 8:17 UTC (3+ messages)
[PATCH 00/32] [PATCH 00/32] drm/i915/display: Add MTL+ platforms to support dpll framework
2025-10-30 7:22 UTC (33+ messages)
` [PATCH 01/32] drm/i915/display: Rename TBT functions to be ICL specific
` [PATCH 02/32] drm/i915/display: Factor out C10 msgbus access start/end helpers
` [PATCH 03/32] drm/i915/display: Sanitize setting the Cx0 PLL use_c10 flag
` [PATCH 04/32] drm/i915/display: Sanitize calculating C20 PLL state from tables
` [PATCH 05/32] drm/i915/display: Track the C20 PHY VDR state in the PLL state
` [PATCH 06/32] drm/i915/display: Move definition of Cx0 PHY functions earlier
` [PATCH 07/32] drm/i915/display: Add macro to get DDI port width from a register value
` [PATCH 08/32] drm/i915/display: Track the Cx0 PHY enabled lane count in the PLL state
` [PATCH 09/32] drm/i915/display: Sanitize C10 PHY PLL SSC register setup
` [PATCH 10/32] drm/i915/display: Read out the Cx0 PHY SSC enabled state
` [PATCH 11/32] drm/i915/display: Determine Cx0 PLL DP mode from PLL state
` [PATCH 12/32] drm/i915/display: Determine Cx0 PLL port clock "
` [PATCH 13/32] drm/i915/display: Zero Cx0 PLL state before compute and HW readout
` [PATCH 14/32] drm/i915/display: Print additional Cx0 PLL HW state
` [PATCH 15/32] drm/i915/display: Remove state verification
` [PATCH 16/32] drm/i915/display: PLL information for MTL+
` [PATCH 17/32] drm/i915/display: Update C10/C20 state calculation
` [PATCH 18/32] drm/i915/display: Compute plls for MTL+ platform
` [PATCH 19/32] drm/i915/display: MTL+ .get_dplls
` [PATCH 20/32] drm/i915/display: MTL+ .put_dplls
` [PATCH 21/32] drm/i915/display: Add .update_active_dpll
` [PATCH 22/32] drm/i915/display: Add .update_dpll_ref_clks
` [PATCH 23/32] drm/i915/display: Add .dump_hw_state
` [PATCH 24/32] drm/i915/display: Add .compare_hw_state
` [PATCH 25/32] drm/i915/display: Add .get_hw_state to MTL+ platforms
` [PATCH 26/32] drm/i915/display: Add .get_freq "
` [PATCH 27/32] drm/i915/display: Add .crtc_get_dpll hook
` [PATCH 28/32] drm/i915/display: PLL verify debug state print
` [PATCH 29/32] drm/i915/display: Add .enable_clock on DDI for MTL+ platforms
` [PATCH 30/32] drm/i915/display: Get configuration for C10 and C20
` [PATCH 31/32] drm/i915/display: Add Thunderbolt support
` [PATCH 32/32] drm/i915/display: Enable dpll framework for MTL+
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