messages from 2025-10-31 10:37:45 to 2025-11-03 13:31:57 UTC [more...]
[PATCH 00/22] vfio: Give VFIO_DEVICE_GET_REGION_INFO its own op
2025-11-03 13:31 UTC (41+ messages)
` [PATCH 01/22] vfio: Provide a get_region_info op
` [PATCH 02/22] vfio/hisi: Convert to the "
` [PATCH 03/22] vfio/virtio: "
` [PATCH 04/22] vfio/nvgrace: "
` [PATCH 05/22] vfio/pci: Fill in the missing get_region_info ops
` [PATCH 06/22] vfio/mtty: Provide a get_region_info op
` [PATCH 07/22] vfio/mdpy: "
` [PATCH 08/22] vfio/mbochs: "
` [PATCH 09/22] vfio/platform: "
` [PATCH 10/22] vfio/fsl: "
` [PATCH 11/22] vfio/cdx: "
` [PATCH 14/22] vfio: Require drivers to implement get_region_info
` [PATCH 15/22] vfio: Add get_region_info_caps op
` [PATCH 19/22] vfio/pci: Convert all PCI drivers to get_region_info_caps
` [PATCH 20/22] vfio/platform: Convert "
` [PATCH 21/22] vfio: Move the remaining drivers "
` [PATCH 22/22] vfio: Remove the get_region_info op
[PATCH next] drm/i915/dmc: Fix extra bracket and wrong variable in PIPEDMC error logs
2025-11-03 13:23 UTC
[PATCH 0/3] replace old wq(s), added WQ_PERCPU to alloc_workqueue
2025-11-03 10:35 UTC (10+ messages)
` [PATCH 1/3] drm/i915: replace use of system_unbound_wq with system_dfl_wq
` [PATCH 2/3] drm/i915: replace use of system_wq with system_percpu_wq
` [PATCH 3/3] drm/i915: WQ_PERCPU added to alloc_workqueue users
[PATCH v2] drm/i915: Setting/clearing the memory access bit when en/disabling i915
2025-11-01 16:02 UTC (2+ messages)
[PATCH v3 0/6] Use display parent interface for runtime pm
2025-11-03 10:16 UTC (4+ messages)
[RESEND, 00/22] Enable/Disable DC balance along with VRR DSB
2025-11-03 10:02 UTC (27+ messages)
` [RESEND, 01/22] drm/i915/display: Add source param for dc balance
` [RESEND, 02/22] drm/i915/dmc: Add pipe dmc registers and bits for DC Balance
` [RESEND, 03/22] drm/i915/vrr: Add VRR DC balance registers
` [RESEND, 04/22] drm/i915/vrr: Add functions to read out vmin/vmax stuff
` [RESEND, 05/22] drm/i915/vrr: Add DC Balance params to crtc_state
` [RESEND, 06/22] drm/i915/vrr: Add state dump for DC Balance params
` [RESEND, 07/22] drm/i915/vrr: Add compute config "
` [RESEND, 08/22] drm/i915/display: Add DC Balance flip counter in crtc
` [RESEND, 09/22] drm/i915/vrr: Increment DC balance flip count on every flip
` [RESEND, 10/22] drm/i915/vrr: Add function to reset DC Balance flip count
` [RESEND, 11/22] drm/i915/vrr: Add function reset DC balance accumulated params
` [RESEND, 12/22] drm/i915/vrr: Write DC balance params to hw registers
` [RESEND, 13/22] drm/i915/vrr: Configure DC balance flipline adjustment
` [RESEND, 14/22] drm/i915/vblank: Extract vrr_vblank_start()
` [RESEND, 15/22] drm/i915/vrr: Implement vblank evasion with DC balancing
` [RESEND, 16/22] drm/i915/display: Wait for VRR PUSH status update
` [RESEND, 17/22] drm/i915/dsb: Add pipedmc dc balance enable/disable
` [RESEND, 18/22] drm/i915/vrr: Pause DC Balancing for DSB commits
` [RESEND, 19/22] drm/i915/display: Add function to configure event for dc balance
` [RESEND, 20/22] drm/i915/vrr: Enable Adaptive sync counter bit
` [RESEND, 21/22] drm/i915/vrr: Enable DC Balance
` [RESEND, 22/22] drm/i915/vrr: Add function to check if DC Balance Possible
` ✗ Fi.CI.BUILD: failure for Enable/Disable DC balance along with VRR DSB
[PATCH v3 0/4] drm: replace drm_print.h includes from headers with a forward declaration
2025-11-03 9:28 UTC (6+ messages)
linux-next: build failure after merge of the drm-misc tree
2025-11-03 9:26 UTC (3+ messages)
` ✗ LGCI.VerificationFailed: failure for "
linux-next: manual merge of the drm-intel tree with the drm-misc tree
2025-11-02 23:22 UTC
linux-next: manual merge of the drm-intel tree with the drm tree
2025-11-02 23:18 UTC
linux-next: manual merge of the drm-intel tree with the drm-misc tree
2025-11-02 23:13 UTC
[PATCH v5 00/25] Enable LT PHY
2025-11-01 13:08 UTC (28+ messages)
` [PATCH v5 01/25] drm/i915/ltphy: Add LT Phy related VDR and Pipe Registers
` [PATCH v5 02/25] drm/i915/cx0: Change register bit naming for powerdown values
` [PATCH v5 03/25] drm/i915/ltphy: Phy lane reset for LT Phy
` [PATCH v5 04/25] drm/i915/cx0: Move the HDMI FRL function to intel_hdmi
` [PATCH v5 05/25] drm/i915/ltphy: Program sequence for PORT_CLOCK_CTL for LT Phy
` [PATCH v5 06/25] drm/i915/ltphy: Add a wrapper for LT Phy powerdown change sequence
` [PATCH v5 07/25] drm/i915/ltphy: Read PHY_VDR_0_CONFIG register
` [PATCH v5 08/25] drm/i915/ltphy: Add LT Phy Programming recipe tables
` [PATCH v5 09/25] drm/i915/ltphy: Program the VDR PLL registers for LT PHY
` [PATCH v5 10/25] drm/i915/ltphy: Update the ltpll config table value for eDP
` [PATCH v5 11/25] drm/i915/ltphy: Enable SSC during port clock programming
` [PATCH v5 12/25] drm/i915/ltphy: Add function to calculate LT PHY port clock
` [PATCH v5 13/25] drm/i915/ltphy: Program the P2P Transaction flow for LT Phy
` [PATCH v5 14/25] drm/i915/ltphy: Program the rest of the PORT_CLOCK_CTL steps
` [PATCH v5 15/25] drm/i915/ltphy: Program the rest of the LT Phy Enable sequence
` [PATCH v5 16/25] drm/i915/ltphy: Program LT Phy Non-TBT PLL disable sequence
` [PATCH v5 17/25] drm/i915/ltphy: Hook up LT Phy Enable & Disable sequences
` [PATCH v5 18/25] drm/i915/ddi: Define LT Phy Swing tables
` [PATCH v5 19/25] drm/i915/ltphy: Program LT Phy Voltage Swing
` [PATCH v5 20/25] drm/i915/ltphy: Enable/Disable Tx after Non TBT Enable sequence
` [PATCH v5 21/25] drm/i915/ltphy: Define the LT Phy state compare function
` [PATCH v5 22/25] drm/i915/ltphy: Define function to readout LT Phy PLL state
` [PATCH v5 23/25] drm/i915/ltphy: Define LT PHY PLL state verify function
` [PATCH v5 24/25] drm/i915/display: Aux Enable and Display powerwell timeouts
` [PATCH v5 25/25] drm/i915/ltphy: Modify the step that need to be skipped
` ✓ i915.CI.BAT: success for Enable LT PHY (rev5)
` ✓ i915.CI.Full: "
[PATCH v2] drm/display/dp: Rename bit 4 of DPCD TEST_REQUEST to match DP2.1 spec
2025-11-01 8:06 UTC (3+ messages)
` ✓ i915.CI.BAT: success for drm/display/dp: Rename bit 4 of DPCD TEST_REQUEST to match DP2.1 spec (rev2)
` ✗ i915.CI.Full: failure "
[PATCH v4 00/25] Enable LT PHY
2025-11-01 3:14 UTC (27+ messages)
` [PATCH v4 01/25] drm/i915/ltphy: Add LT Phy related VDR and Pipe Registers
` [PATCH v4 02/25] drm/i915/cx0: Change register bit naming for powerdown values
` [PATCH v4 03/25] drm/i915/ltphy: Phy lane reset for LT Phy
` [PATCH v4 04/25] drm/i915/cx0: Move the HDMI FRL function to intel_hdmi
` [PATCH v4 05/25] drm/i915/ltphy: Program sequence for PORT_CLOCK_CTL for LT Phy
` [PATCH v4 06/25] drm/i915/ltphy: Add a wrapper for LT Phy powerdown change sequence
` [PATCH v4 07/25] drm/i915/ltphy: Read PHY_VDR_0_CONFIG register
` [PATCH v4 08/25] drm/i915/ltphy: Add LT Phy Programming recipe tables
` [PATCH v4 09/25] drm/i915/ltphy: Program the VDR PLL registers for LT PHY
` [PATCH v4 10/25] drm/i915/ltphy: Update the ltpll config table value for eDP
` [PATCH v4 11/25] drm/i915/ltphy: Enable SSC during port clock programming
` [PATCH v4 12/25] drm/i915/ltphy: Add function to calculate LT PHY port clock
` [PATCH v4 13/25] drm/i915/ltphy: Program the P2P Transaction flow for LT Phy
` [PATCH v4 14/25] drm/i915/ltphy: Program the rest of the PORT_CLOCK_CTL steps
` [PATCH v4 15/25] drm/i915/ltphy: Program the rest of the LT Phy Enable sequence
` [PATCH v4 16/25] drm/i915/ltphy: Program LT Phy Non-TBT PLL disable sequence
` [PATCH v4 17/25] drm/i915/ltphy: Hook up LT Phy Enable & Disable sequences
` [PATCH v4 18/25] drm/i915/ddi: Define LT Phy Swing tables
` [PATCH v4 19/25] drm/i915/ltphy: Program LT Phy Voltage Swing
` [PATCH v4 20/25] drm/i915/ltphy: Enable/Disable Tx after Non TBT Enable sequence
` [PATCH v4 21/25] drm/i915/ltphy: Define the LT Phy state compare function
` [PATCH v4 22/25] drm/i915/ltphy: Define function to readout LT Phy PLL state
` [PATCH v4 23/25] drm/i915/ltphy: Define LT PHY PLL state verify function
` [PATCH v4 24/25] drm/i915/display: Aux Enable and Display powerwell timeouts
` [PATCH v4 25/25] drm/i915/ltphy: Modify the step that need to be skipped
` ✗ Fi.CI.BUILD: failure for Enable LT PHY (rev4)
[PATCH v2 00/32] drm/i915/display: Add initial support for Xe3p_LPD
2025-10-31 22:41 UTC (9+ messages)
` [PATCH v2 11/32] drm/i915/xe3p_lpd: Underrun debuggability and error codes/hints
` [PATCH v2 19/32] drm/i915/xe3p_lpd: PSR SU minimum lines is 4
[PULL] drm-intel-gt-next
2025-10-31 21:02 UTC (2+ messages)
[PATCH] drm/i915/gem: Fix NULL pointer dereference in eb_release_vmas()
2025-10-31 20:30 UTC (6+ messages)
` ✓ i915.CI.BAT: success for "
` ✗ i915.CI.Full: failure "
[CI 00/32] [PATCH 00/32] drm/i915/display: Add MTL+ platforms to support dpll framework
2025-10-31 19:57 UTC (35+ messages)
` [CI 01/32] drm/i915/display: Rename TBT functions to be ICL specific
` [CI 02/32] drm/i915/display: Factor out C10 msgbus access start/end helpers
` [CI 03/32] drm/i915/display: Sanitize setting the Cx0 PLL use_c10 flag
` [CI 04/32] drm/i915/display: Sanitize calculating C20 PLL state from tables
` [CI 05/32] drm/i915/display: Track the C20 PHY VDR state in the PLL state
` [CI 06/32] drm/i915/display: Move definition of Cx0 PHY functions earlier
` [CI 07/32] drm/i915/display: Add macro to get DDI port width from a register value
` [CI 08/32] drm/i915/display: Track the Cx0 PHY enabled lane count in the PLL state
` [CI 09/32] drm/i915/display: Sanitize C10 PHY PLL SSC register setup
` [CI 10/32] drm/i915/display: Read out the Cx0 PHY SSC enabled state
` [CI 11/32] drm/i915/display: Determine Cx0 PLL DP mode from PLL state
` [CI 12/32] drm/i915/display: Determine Cx0 PLL port clock "
` [CI 13/32] drm/i915/display: Zero Cx0 PLL state before compute and HW readout
` [CI 14/32] drm/i915/display: Print additional Cx0 PLL HW state
` [CI 15/32] drm/i915/display: Remove state verification
` [CI 16/32] drm/i915/display: PLL information for MTL+
` [CI 17/32] drm/i915/display: Update C10/C20 state calculation
` [CI 18/32] drm/i915/display: Compute plls for MTL+ platform
` [CI 19/32] drm/i915/display: MTL+ .get_dplls
` [CI 20/32] drm/i915/display: MTL+ .put_dplls
` [CI 21/32] drm/i915/display: Add .update_active_dpll
` [CI 22/32] drm/i915/display: Add .update_dpll_ref_clks
` [CI 23/32] drm/i915/display: Add .dump_hw_state
` [CI 24/32] drm/i915/display: Add .compare_hw_state
` [CI 25/32] drm/i915/display: Add .get_hw_state to MTL+ platforms
` [CI 26/32] drm/i915/display: Add .get_freq "
` [CI 27/32] drm/i915/display: Add .crtc_get_dpll hook
` [CI 28/32] drm/i915/display: PLL verify debug state print
` [CI 29/32] drm/i915/display: Add .enable_clock on DDI for MTL+ platforms
` [CI 30/32] drm/i915/display: Get configuration for C10 and C20
` [CI 31/32] drm/i915/display: Add Thunderbolt support
` [CI 32/32] drm/i915/display: Enable dpll framework for MTL+
` ✓ i915.CI.BAT: success for drm/i915/display: Add MTL+ platforms to support dpll framework (rev2)
` ✗ i915.CI.Full: failure "
[PATCH 0/3] drm/displayid: quirk incorrect DisplayID checksums
2025-10-31 19:29 UTC (3+ messages)
` ✓ i915.CI.BAT: success for drm/displayid: quirk incorrect DisplayID checksums (rev2)
` ✓ i915.CI.Full: "
[PULL] drm-xe-fixes
2025-10-31 18:13 UTC (2+ messages)
[PULL] drm-misc-fixes
2025-10-31 18:10 UTC (2+ messages)
[PULL] drm-intel-fixes
2025-10-31 18:09 UTC (2+ messages)
[PULL] drm-misc-next
2025-10-31 17:53 UTC (2+ messages)
[PULL] drm-xe-next
2025-10-31 17:46 UTC (2+ messages)
[PATCH] drm/i915/rom: convert intel_rom interfaces to struct drm_device
2025-10-31 16:53 UTC (2+ messages)
` ✗ Fi.CI.BUILD: failure for drm/i915/rom: convert intel_rom interfaces to struct drm_device (rev2)
[PATCH] drm/i915/dmabuf: Flush the cache in vmap
2025-10-31 16:50 UTC (12+ messages)
[PATCH v3 00/25] Enable LT PHY
2025-10-31 13:35 UTC (10+ messages)
` [PATCH v3 12/25] drm/i915/ltphy: Add function to calculate LT PHY port clock
` [PATCH v3 20/25] drm/i915/ltphy: Enable/Disable Tx after Non TBT Enable sequence
` [PATCH v3 21/25] drm/i915/ltphy: Define the LT Phy state compare function
` [PATCH v3 22/25] drm/i915/ltphy: Define function to readout LT Phy PLL state
` [PATCH v3 23/25] drm/i915/ltphy: Define LT PHY PLL state verify function
` [PATCH v3 24/25] drm/i915/display: Aux Enable and Display powerwell timeouts
` [PATCH v3 25/25] drm/i915/ltphy: Modify the step that need to be skipped
` ✗ Fi.CI.BUILD: failure for Enable LT PHY (rev3)
[PATCH 0/3] drm/1915/dram: Fix DIMM_S decoding on ICL
2025-10-31 11:53 UTC (2+ messages)
` ✓ i915.CI.Full: success for "
[PATCH v2 0/4] drm/i915/x3p_lpd: FBC related patches
2025-10-31 11:37 UTC (4+ messages)
` [PATCH v2 4/4] drm/i915/xe3p_lpd: use pixel normalizer for fp16 formats for FBC
[PATCH 0/6] drm/i915: i915_utils.h refactoring
2025-10-31 11:26 UTC (6+ messages)
` [PATCH 3/6] drm/i915/display: add intel_display_run_as_guest()
[PATCH v2 1/2] drm/i915/dsi: log send packet sequence errors
2025-10-31 11:06 UTC (3+ messages)
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