messages from 2025-11-17 07:36:17 to 2025-11-19 12:00:01 UTC [more...]
[PATCH v4 00/10] Add new general DRM property "color format"
2025-11-19 9:10 UTC (16+ messages)
` [PATCH v4 02/10] drm: "
` [PATCH v4 03/10] drm: Add enum conversion from/to HDMI_COLORSPACE to DRM_COLOR_FORMAT
` [PATCH v4 04/10] drm/bridge: Act on the DRM color format property
` [PATCH v4 05/10] drm/bridge: dw-hdmi-qp: Set bridge supported_formats
` [PATCH v4 06/10] drm/rockchip: dw_hdmi_qp: Set supported_formats platdata
` [PATCH v4 07/10] drm/display: hdmi-state-helper: Act on color format DRM property
` [PATCH v4 10/10] drm/rockchip: Implement "color format" "
REGRESSION on linux-next (next-20251106)
2025-11-19 9:31 UTC (20+ messages)
` ✗ Fi.CI.BUILD: failure for "
[PATCH v2 00/32] drm/i915/cx0: Add MTL+ platforms to support dpll framework
2025-11-19 11:59 UTC (59+ messages)
` [PATCH v2 01/32] drm/i915/cx0: Rename TBT functions to be ICL specific
` [PATCH v2 02/32] drm/i915/cx0: Factor out C10 msgbus access start/end helpers
` [PATCH v2 03/32] drm/i915/cx0: Sanitize setting the Cx0 PLL use_c10 flag
` [PATCH v2 04/32] drm/i915/cx0: Sanitize calculating C20 PLL state from tables
` [PATCH v2 05/32] drm/i915/cx0: Track the C20 PHY VDR state in the PLL state
` [PATCH v2 06/32] drm/i915/cx0: Move definition of Cx0 PHY functions earlier
` [PATCH v2 07/32] drm/i915/cx0: Add macro to get DDI port width from a register value
` [PATCH v2 08/32] drm/i915/cx0: Track the Cx0 PHY enabled lane count in the PLL state
` [PATCH v2 09/32] drm/i915/cx0: Sanitize C10 PHY PLL SSC register setup
` [PATCH v2 10/32] drm/i915/cx0: Read out the Cx0 PHY SSC enabled state
` [PATCH v2 11/32] drm/i915/cx0: Determine Cx0 PLL DP mode from PLL state
` [PATCH v2 12/32] drm/i915/cx0: Determine Cx0 PLL port clock "
` [PATCH v2 13/32] drm/i915/cx0: Zero Cx0 PLL state before compute and HW readout
` [PATCH v2 14/32] drm/i915/cx0: Print additional Cx0 PLL HW state
` [PATCH v2 15/32] drm/i915/cx0: Remove state verification
` [PATCH v2 16/32] drm/i915/cx0: Add PLL information for MTL+
` [PATCH v2 17/32] drm/i915/cx0: Update C10/C20 state calculation
` [PATCH v2 18/32] drm/i915/cx0: Compute plls for MTL+ platform
` [PATCH v2 19/32] drm/i915/cx0: Add MTL+ .get_dplls hook
` [PATCH v2 20/32] drm/i915/cx0: Add MTL+ .put_dplls hook
` [PATCH v2 21/32] drm/i915/cx0: Add MTL+ .update_active_dpll hook
` [PATCH v3 "
` [PATCH v2 22/32] drm/i915/cx0: Add MTL+ .update_dpll_ref_clks hook
` [PATCH v2 23/32] drm/i915/cx0: Add MTL+ .dump_hw_state hook
` [PATCH v2 24/32] drm/i915/cx0: Add .compare_hw_state hook
` [PATCH v2 25/32] drm/i915/cx0: Add MTL+ .get_hw_state hook
` [PATCH v2 26/32] drm/i915/cx0: Add MTL+ .get_freq hook
` [PATCH v2 27/32] drm/i915/cx0: Add MTL+ .crtc_get_dpll hook
` [PATCH v2 28/32] drm/i915/cx0: PLL verify debug state print
` [PATCH v2 29/32] drm/i915/cx0: Add MTL+ .enable_clock/.disable clock hooks on DDI
` [PATCH v2 30/32] drm/i915/cx0: Get encoder configuration for C10 and C20 PHY PLLs
` [PATCH v2 31/32] drm/i915/cx0: Add MTL+ Thunderbolt PLL hooks
` [PATCH v2 32/32] drm/i915/cx0: Enable dpll framework for MTL+
` [PATCH v3 "
` ✗ i915.CI.BAT: failure for drm/i915/cx0: Add MTL+ platforms to support dpll framework
` ✓ i915.CI.BAT: success for drm/i915/cx0: Add MTL+ platforms to support dpll framework (rev4)
` ✓ i915.CI.Full: "
[PATCH i-g-t 0/3] tests/intel/gem_eio: Avoid skips in stress subtests
2025-11-19 10:57 UTC (4+ messages)
` [PATCH i-g-t 1/3] tests/intel/gem_eio: Fix mistyped symbol
` [PATCH i-g-t 2/3] tests/intel/gem_eio: Convert stress subtests to dynamic
` [PATCH i-g-t 3/3] tests/intel/gem_eio: Avoid skips in stress subtests
[PATCH] drm/display/dp_mst: Add protection against 0 vcpi
2025-11-19 11:01 UTC (12+ messages)
` [PATCH v2] "
` ✓ i915.CI.BAT: success for drm/display/dp_mst: Add protection against 0 vcpi (rev2)
[RFC PATCH] drm/i915: Use rcu_dereference() in hwsp_offset()
2025-11-19 10:29 UTC (2+ messages)
` ✗ i915.CI.BAT: failure for drm/i915: Use rcu_dereference() in hwsp_offset() (rev2)
[PATCH v2] drm/buddy: Mark drm_test_buddy_fragmentation_performance test as slow
2025-11-19 9:33 UTC (2+ messages)
[v6 00/16] Plane Color Pipeline support for Intel platforms
2025-11-19 8:14 UTC (27+ messages)
` [v6 03/16] drm/i915: Add intel_color_op
` [v6 04/16] drm/i915/color: Add helper to create intel colorop
` [v6 05/16] drm/i915/color: Create a transfer function color pipeline
` [v6 06/16] drm/i915/color: Add framework to program CSC
` [v6 07/16] drm/i915/color: Preserve sign bit when int_bits is Zero
` [v6 09/16] drm/i915: Add register definitions for Plane Degamma
` [v6 10/16] drm/i915/color: Add framework to program PRE/POST CSC LUT
` [v6 12/16] drm/i915/color: Program Pre-CSC registers
` [v6 14/16] drm/i915/display: Add registers for 3D LUT
` [v6 15/16] drm/i915/color: Add 3D LUT to color pipeline
` [v6 16/16] drm/i915/color: Enable Plane Color Pipelines
[PATCH 0/3] drm/1915/dram: Fix DIMM_S decoding on ICL
2025-11-19 8:05 UTC (5+ messages)
` [PATCH 3/3] drm/i915/dram: Fix ICL DIMM_S decoding
[PATCH v3] drm/i915: Use symmetric free for vma resources
2025-11-18 21:43 UTC (3+ messages)
` ✓ i915.CI.BAT: success for drm/i915: Use symmetric free for vma resources (rev2)
` ✗ i915.CI.Full: failure "
[PATCH] drm/i915/display: change pipe order for platforms with big joiner
2025-11-18 19:34 UTC (7+ messages)
` ✗ i915.CI.BAT: failure for "
` [PATCH v2] "
` ✗ i915.CI.BAT: failure for drm/i915/display: change pipe order for platforms with big joiner (rev2)
[PATCH v2] drm/i915/selftests: Defer signalling the request fence
2025-11-18 17:20 UTC (3+ messages)
` ✓ i915.CI.BAT: success for drm/i915/selftests: Defer signalling the request fence (rev4)
` ✗ i915.CI.Full: failure "
[PATCH] drm/i915/gem: Fix NULL pointer dereference in eb_release_vmas()
2025-11-18 15:04 UTC (3+ messages)
` ✓ i915.CI.BAT: success for drm/i915/gem: Fix NULL pointer dereference in eb_release_vmas() (rev2)
` ✓ i915.CI.Full: "
[PATCH] drm/i915/selftests: Defer signalling the request fence
2025-11-18 14:04 UTC (3+ messages)
[PATCH v2] drm/i915: Use symmetric free for vma resources
2025-11-18 13:57 UTC (3+ messages)
` ✗ LGCI.VerificationFailed: failure for "
[CI 00/10] drm/i915: call irq and rps through the parent interface
2025-11-18 13:53 UTC (17+ messages)
` [CI 01/10] drm/{i915, xe}/display: duplicate gen2 irq/error init/reset in display irq
` [CI 02/10] drm/i915/display: convert the display irq interfaces to struct intel_display
` [CI 03/10] drm/{i915,xe}/display: move irq calls to parent interface
` [CI 04/10] drm/i915: add .vgpu_active "
` [CI 05/10] drm/i915: add .has_fenced_regions "
` [CI 06/10] drm/i915/rps: store struct dma_fence in struct wait_rps_boost
` [CI 07/10] drm/i915/rps: call RPS functions via the parent interface
` [CI 08/10] drm/i915/rps: postpone i915 fence check to boost
` [CI 09/10] drm/i915: add .fence_priority_display to parent interface
` [CI 10/10] drm/xe/rps: build RPS as part of xe
` ✗ i915.CI.BAT: failure for drm/i915: call irq and rps through the parent interface (rev5)
` ✗ i915.CI.BAT: failure for drm/i915: call irq and rps through the parent interface (rev6)
` ✓ i915.CI.BAT: success "
` ✗ i915.CI.Full: failure "
[PATCH v4 00/10] Enable DP2.1 alpm
2025-11-18 11:06 UTC (13+ messages)
` [PATCH v4 02/10] drm/i915/alpm: alpm_init() for DP2.1
` [PATCH v4 05/10] drm/i915/alpm: Auxless wake time calculation for Xe3p
` [PATCH v4 06/10] drm/i915/alpm: Half LFPS cycle calculation
` [PATCH v4 07/10] drm/i915/alpm: Program LTTPR count for DP 2.1 ALPM
[PATCH v2] drm/i915/fbc: Apply wa_15018326506
2025-11-18 9:32 UTC (3+ messages)
[PULL] drm-xe-next
2025-11-18 8:34 UTC (3+ messages)
[PATCH v3 00/14] Remove redundant rcu_read_lock/unlock() in spin_lock
2025-11-18 7:24 UTC (4+ messages)
` [PATCH v3 14/14] wifi: ath9k: "
[RFC 0/8] CMTG enablement
2025-11-18 1:00 UTC (15+ messages)
` [RFC 1/8] drm/i915/cmtg: enable cmtg LNL onwards
` [RFC 2/8] drm/i915/cmtg: cmtg set clock select
` [RFC 3/8] drm/i915/cmtg: set timings for cmtg
` [RFC 4/8] drm/i915/cmtg: program vrr registers of cmtg
` [RFC 5/8] drm/i915/cmtg: program set context latency "
` [RFC 6/8] drm/i915/cmtg: set transcoder mn for cmtg
` [RFC 7/8] drm/i915/cmtg: program sync to port "
` [RFC 8/8] drm/i915/cmtg: enable cmtg ctl
` ✓ i915.CI.BAT: success for CMTG enablement
` ✓ i915.CI.Full: "
[PATCH v4 00/11] drm/i915/display: Add initial support for Xe3p_LPD
2025-11-17 17:58 UTC (12+ messages)
` [PATCH v4 07/11] drm/i915/xe3p_lpd: Extend Type-C flow for static DDI allocation
[PATCH v2] drm/i915/xe3p_lpd: Enable display use of system cache for FBC
2025-11-17 17:41 UTC (2+ messages)
[PATCH] drm/i915: Fix improper freeing of GTT resources
2025-11-13 6:28 UTC (2+ messages)
[PATCH 0/1] drm/i915/display: Add quirk to force backlight type on some TUXEDO devices
2025-11-14 18:43 UTC (3+ messages)
` [PATCH 1/1] "
[PATCH v2 00/11] PCI: BAR resizing fix/rework
2025-11-14 14:35 UTC (9+ messages)
` [PATCH v2 03/11] PCI: Change pci_dev variable from 'bridge' to 'dev'
` [PATCH v2 08/11] drm/xe: Remove driver side BAR release before resize
Cache coherency issues when reading from intel Xe buffer
2025-11-14 9:36 UTC (4+ messages)
[PATCH] i915/display/intel_ddi: Reduce severity of failed FEC enabling
2025-11-17 13:19 UTC (3+ messages)
` ✓ i915.CI.BAT: success for i915/display/intel_ddi: Reduce severity of failed FEC enabling (rev2)
` ✓ i915.CI.Full: "
[PATCH i-g-t v2] tests/intel/gem_lmem_swapping: Run smem-oom helper loop in background
2025-11-17 11:29 UTC
[PATCH v8 00/18] Enable/Disable DC balance along with VRR DSB
2025-11-17 10:43 UTC (2+ messages)
` ✓ i915.CI.Full: success for "
[PATCH v2] drm/fb-helper: Allocate and release fb_info in single place
2025-11-17 10:19 UTC (2+ messages)
[PATCH 0/5] LOBF fixes
2025-11-17 7:36 UTC (4+ messages)
` [PATCH 4/5] drm/i915/alpm: Simplify and align LOBF checks in pre/post plane update
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