messages from 2026-06-15 14:08:08 to 2026-06-16 14:53:29 UTC [more...]
[PATCH v2 00/11] Enable CMRR in fixed-RR VRR path
2026-06-16 14:42 UTC (10+ messages)
` [PATCH v2 01/11] drm/i915/vrr: add per-CRTC vrr/cmrr debugfs control
` [PATCH v2 02/11] drm/i915/vrr: compute CMRR fractional timings generically
` [PATCH v2 03/11] drm/i915/vrr: dump CMRR state in the crtc state dump
` [PATCH v2 04/11] drm/i915/vrr: Move CMRR hw registers to fix refresh rate path
` [PATCH v2 05/11] drm/i915/vrr: Enable/Disable CMRR based on enable/disable preconditions
` [PATCH v2 06/11] drm/i915/display: Move CMRR crtc_state members under VRR
` [PATCH v2 07/11] drm/i915/vrr: Fix the CMRR enabling/disabling sequence
` [PATCH v2 08/11] drm/i915/vrr: Compare state and HW registers if platform supports CMRR
` [PATCH v2 09/11] drm/i915/vrr: Remove TODO as CMRR is exclusive to Adaptive mode
[CI v4 00/39] For CI only: DC3CO/CMTG validation series
2026-06-16 13:37 UTC (41+ messages)
` [CI v4 01/39] drm/i915/cmtg: Add intel_cmtg_is_allowed() for CMTG
` [CI v4 02/39] drm/i915/cmtg: Set CMTG clock select
` [CI v4 03/39] drm/i915/cmtg: Add CMTG transcoder offset in struct _device_info
` [CI v4 04/39] drm/i915/display: Pass target transcoder to intel_set_transcoder_timings()
` [CI v4 05/39] drm/i915/display: Rename cpu_transcoder parameter to transcoder
` [CI v4 06/39] drm/i915/display: Skip DP_MIN_HBLANK_CTL programming for CMTG transcoders
` [CI v4 07/39] drm/i915/display: Pass transcoder to intel_set_transcoder_timings_lrr()
` [CI v4 08/39] drm/i915/display: Rename cpu_transcoder parameter to transcoder in LRR path
` [CI v4 09/39] drm/i915/cmtg: Set timings for CMTG by using transcoder timing helpers
` [CI v4 10/39] drm/i915/vrr: Pass transcoder to intel_vrr_set_fixed_rr_timings()
` [CI v4 11/39] drm/i915/display: Rename cpu_transcoder parameter to transcoder in VRR fixed-rr path
` [CI v4 12/39] drm/i915/cmtg: Program VRR fixed-rate timings for CMTG transcoder
` [CI v4 13/39] drm/i915/cmtg: Program VRR control register "
` [CI v4 14/39] drm/i915/cmtg: Set link M/N "
` [CI v4 15/39] drm/i915/cmtg: Add hook to enable CMTG with sync to port
` [CI v4 16/39] drm/i915/cmtg: Add a hook to make eDP transcoder secondary
` [CI v4 17/39] drm/i915/cmtg: Modify existing hook to disable CMTG
` [CI v4 18/39] drm/i915/cmtg: Add CMTG HWGB programming
` [CI v4 19/39] drm/i915/cmtg: Add CMTG scan line programming
` [CI v4 20/39] drm/i915/cmtg: Add trigger to enable/disable cmtg
` [CI v4 21/39] drm/i915/cmtg: Restore CMTG after DC6 exit
` [CI v4 22/39] drm/i915/cmtg: Add CMTG interrupt handling
` [CI v4 23/39] drm/i915/display: Remove TGL DC3CO support
` [CI v4 24/39] drm/i915/display: Switch DC3CO enable from standalone bit to DC level encoding
` [CI v4 25/39] drm/i915/display: Use FIELD_PREP() for DC state enable bits
` [CI v4 26/39] drm/i915/display: Add DC3CO DC_STATE enable/disable support
` [CI v4 27/39] drm/i915/display: Add HAS_DC3CO() macro
` [CI v4 28/39] drm/i915/display: Add DC3CO support check
` [CI v4 29/39] drm/i915/psr: Add psr2 deep sleep helper API
` [CI v4 30/39] drm/i915/display: Add DC3CO compute and set target state in commit tail
` [CI v4 31/39] drm/i915/display: Store DC3CO eligibility in PSR state
` [CI v4 32/39] drm/i915/display: PSR2: Set idle_frames to 0 for DC3CO
` [CI v4 33/39] drm/i915/display: Enable DC3CO idle protocol in ALPM
` [CI v4 34/39] drm/i915/display: PSR Add delayed work to exit DC3CO
` [CI v4 35/39] drm/i915/display: Add helper to enable DC counter
` [CI v4 36/39] drm/i915/display: Add DC3CO count and residency in dmc debugfs
` [CI v4 37/39] drm/i915/display: Guard CMTG function calls
` [CI v4 38/39] drm/i915/display: Enable DC3CO DC state
` [CI v4 39/39] drm/i915/display: Mask RO bits in gen9_write_dc_state()
` ✗ Fi.CI.BUILD: failure for For CI only: DC3CO/CMTG validation series (rev5)
[PATCH v1] drm/i915/display: Program TRANS_VTOTAL from mode vtotal
2026-06-16 13:31 UTC (4+ messages)
` ✗ i915.CI.BAT: failure for "
[PATCH v8 00/27] drm/i915/display: All patches to make PREEMPT_RT work on i915 + xe
2026-06-16 13:17 UTC (30+ messages)
` [PATCH v8 01/27] drm/vblank_work: Add methods to schedule vblank_work in 2 stages
` [PATCH v8 02/27] drm/vblank: Add a 2-stage version of drm_crtc_arm_vblank_event
` [PATCH v8 03/27] drm/intel/display: Make intel_crtc_arm_vblank_event static
` [PATCH v8 04/27] drm/intel/display: Convert vblank event handling to 2-stage arming
` [PATCH v8 05/27] drm/i915/display: Move vblank put until after critical section
` [PATCH v8 06/27] drm/i915/display: Remove locking from intel_vblank_evade "
` [PATCH v8 07/27] drm/i915/display: Handle vlv dsi workaround in scanline_in_safe_range too
` [PATCH v8 08/27] drm/i915: Use preempt_disable/enable_rt() where recommended
` [PATCH v8 09/27] drm/i915/display: Make get_vblank_counter use intel_de_read_fw()
` [PATCH v8 10/27] drm/i915/display: Do not take uncore lock in i915_get_vblank_counter
` [PATCH v8 11/27] drm/i915/display: Make icl_dsi_frame_update use _fw too
` [PATCH v8 12/27] drm/i915/display: Use intel_de_read/write_fw in colorops
` [PATCH v8 13/27] drm/i915/display: Use intel_de_write_fw in intel_pipe_fastset
` [PATCH v8 14/27] drm/i915/display: Make set_pipeconf use the fw variants
` [PATCH v8 15/27] drm/i915/gt: Use spin_lock_irq() instead of local_irq_disable() + spin_lock()
` [PATCH v8 16/27] drm/i915: Drop the irqs_disabled() check
` [PATCH v8 17/27] drm/i915/guc: Consider also RCU depth in busy loop
` [PATCH v8 18/27] drm/i915/gt: Fix selftests on PREEMPT_RT
` [PATCH v8 19/27] drm/i915/gt: Set stop_timeout() correctly on PREEMPT-RT
` [PATCH v8 20/27] drm/i915/display: Remove uncore lock from vlv_atomic_update_fifo
` [PATCH v8 21/27] drm/i915: Use sleeping selftests for igt_atomic on PREEMPT_RT
` [PATCH v8 22/27] Revert "drm/i915: Depend on !PREEMPT_RT."
` [PATCH v8 23/27] PREEMPT_RT injection
` [PATCH v8 24/27] FOR-CI: bump MAX_STACK_TRACE_ENTRIES
` [PATCH v8 25/27] drm/i915/gt: Add a spinlock to prevent starvation of irq_work
` [PATCH v8 26/27] drm/xe/display: Always use system memory on PREEMPT_RT for DPT
` [PATCH v8 27/27] drm/xe/display: Prefer not to allocate a framebuffers in stolen memory
` ✗ i915.CI.BAT: failure for drm/i915/display: All patches to make PREEMPT_RT work on i915 + xe. (rev16)
` ✓ i915.CI.BAT: success "
[PATCH v2 0/2] Unify fec enable/disable across the mst streams
2026-06-16 12:57 UTC (8+ messages)
` [PATCH v2 1/2] drm/i915/mst: Unify fec_enable across "
` [PATCH v2 2/2] drm/i915/display: Refcount for fec enable/disable
` ✓ i915.CI.BAT: success for Unify fec enable/disable across the mst streams
[PATCH v9 00/22] CMTG enablement
2026-06-16 12:56 UTC (32+ messages)
` [PATCH v9 01/22] drm/i915/cmtg: Add intel_cmtg_is_allowed() for CMTG
` [PATCH v9 02/22] drm/i915/cmtg: Set CMTG clock select
` [PATCH v9 03/22] drm/i915/cmtg: Add CMTG transcoder offset in struct _device_info
` [PATCH v9 04/22] drm/i915/display: Pass target transcoder to intel_set_transcoder_timings()
` [PATCH v9 06/22] drm/i915/display: Skip DP_MIN_HBLANK_CTL programming for CMTG transcoders
` [PATCH v9 07/22] drm/i915/display: Pass transcoder to intel_set_transcoder_timings_lrr()
` [PATCH v9 08/22] drm/i915/display: Rename cpu_transcoder parameter to transcoder in LRR path
` [PATCH v9 09/22] drm/i915/cmtg: Set timings for CMTG by using transcoder timing helpers
` [PATCH v9 10/22] drm/i915/vrr: Pass transcoder to intel_vrr_set_fixed_rr_timings()
` [PATCH v9 11/22] drm/i915/display: Rename cpu_transcoder parameter to transcoder in VRR fixed-rr path
` [PATCH v9 12/22] drm/i915/cmtg: Program VRR fixed-rate timings for CMTG transcoder
` [PATCH v9 13/22] drm/i915/cmtg: Program VRR control register "
` [PATCH v9 14/22] drm/i915/cmtg: Set link M/N "
` [PATCH v9 15/22] drm/i915/cmtg: Add hook to enable CMTG with sync to port
` [PATCH v9 16/22] drm/i915/cmtg: Add a hook to make eDP transcoder secondary
` [PATCH v9 17/22] drm/i915/cmtg: Modify existing hook to disable CMTG
` [PATCH v9 18/22] drm/i915/cmtg: Add CMTG HWGB programming
` [PATCH v9 19/22] drm/i915/cmtg: Add CMTG scan line programming
` [PATCH v9 20/22] drm/i915/cmtg: Add trigger to enable/disable cmtg
` [PATCH v9 21/22] drm/i915/cmtg: Restore CMTG after DC6 exit
` [PATCH v9 22/22] drm/i915/cmtg: Add CMTG interrupt handling
` ✓ i915.CI.BAT: success for CMTG enablement (rev9)
` [PATCH v9 05/22] drm/i915/display: Rename cpu_transcoder parameter to transcoder
` ✓ i915.CI.Full: success for CMTG enablement (rev9)
[PATCH v2] drm/i915/alpm: Move the check for PSR and Fixed RR in compute_config_late
2026-06-16 12:33 UTC (3+ messages)
` ✓ i915.CI.BAT: success for drm/i915/alpm: Move the check for PSR and Fixed RR in compute_config_late (rev2)
[PATCH] drm/i915/display: update to the BW buddy configuration
2026-06-16 12:27 UTC (2+ messages)
` ✗ i915.CI.BAT: failure for "
[PATCH] drm/i915/backlight: Set brightness to 0 on disable
2026-06-16 11:50 UTC (2+ messages)
` ✓ i915.CI.BAT: success for "
[PATCH 0/4] drm/{i915,xe}: unify runtime pm calls
2026-06-16 10:09 UTC (10+ messages)
` [PATCH 2/4] drm/{i915, xe}: add new intel_display_driver_runtime_pm_{enable, disable}()
` [PATCH 2/4] drm/{i915,xe}: add new intel_display_driver_runtime_pm_{enable,disable}()
` [PATCH 3/4] drm/xe/display: separate d3cold handling from xe_display_pm_runtime_suspend_late()
` [PATCH 4/4] drm/xe/display: unify runtime suspend/resume with i915 for non-d3cold
` ✓ i915.CI.BAT: success for drm/{i915,xe}: unify runtime pm calls
` ✗ i915.CI.Full: failure "
[PATCH v3 0/7] drm/i915/display: reduce the pm demand peak bw based on display data rate
2026-06-16 9:58 UTC (10+ messages)
` [PATCH v3 1/7] drm/i915/wm: clear the plane ddb_y entries on plane disable
` [PATCH v3 2/7] drm/i915/pm_demand: introduce HAS_PMDEMAND macro
` [PATCH v3 3/7] drm/i915/display: sagv pre/post plane calls to check pmdemand support
` [PATCH v3 4/7] drm/i915/bw: Extract icl_init_qgv_info()
` [PATCH v3 5/7] drm/i915/bw: extract update_sagv_status()
` [PATCH v3 6/7] drm/i915/bw: avoid replicating the update_sagv_status() calls
` [PATCH v3 7/7] drm/i915/bw: introduce the peak bandwidth threshold
` ✓ i915.CI.BAT: success for drm/i915/display: reduce the pm demand peak bw based on display data rate (rev2)
` ✓ i915.CI.Full: "
Three monitors on HD4000
2026-06-16 9:49 UTC (2+ messages)
[PATCH] drm/intel: drop driver include from mchbar_regs.h
2026-06-16 9:44 UTC (5+ messages)
` ✓ i915.CI.BAT: success for "
` ✗ i915.CI.Full: failure "
[PATCH 0/6] drm/i915/cdclk: CDCLK sanitization stuff
2026-06-16 8:26 UTC (13+ messages)
` [PATCH 1/6] drm/i915/cdclk: Fix up CDCLK_FREQ_DECIMAL without a full PLL re-enable
` [PATCH 2/6] drm/i915/cdclk: Print the reason for the CDCLK sanitization
` [PATCH 3/6] drm/i915/cdclk Clean up CDCLK_CTL defines
` [PATCH 4/6] drm/i915/cdclk: Document CDCLK_CTL bits
` [PATCH 5/6] drm/i915/cdclk: Introduce bxt_cdclk_cd2x_pipe_mask() and use it
` [PATCH 6/6] drm/i915/cdclk: Use the TGL+ CD2x pipe select bits also on ICL
[PATCH] drm/i915/alpm: Move the check for PSR and Fixed RR in compute_config_late
2026-06-16 8:22 UTC (3+ messages)
[PATCH] drm/i915/drrs: Synchronize drrs activate with debugfs
2026-06-16 8:05 UTC (2+ messages)
[PATCH 0/4] drm/i915: Work harder to enable VRR based refresh rate changes on eDP
2026-06-16 7:21 UTC (7+ messages)
[PATCH] drm/i915/display: Refcount for fec enable/disable
2026-06-16 5:46 UTC (5+ messages)
[PATCH v2 0/3] drm/i915/scaler: allocation cleanup
2026-06-16 5:32 UTC (6+ messages)
` [PATCH v2 1/3] drm/i915/scaler: remove unused plane_state argument
` [PATCH v2 2/3] drm/i915/scaler: s/i/scaler_id/ again
` [PATCH v2 3/3] drm/i915/scaler: return -EINVAL instead of -1
` ✓ i915.CI.BAT: success for drm/i915/scaler: allocation cleanup (rev2)
` ✗ i915.CI.Full: failure "
[PATCH 0/6] drm/{i915, xe}: display probe/remove cleanup and unification
2026-06-16 4:39 UTC (9+ messages)
` [PATCH 1/6] drm/i915: move intel_display_device_probe() call a level higher
` [PATCH 2/6] drm/i915: remove superfluous checks for pdev->msi_enabled
` [PATCH 3/6] drm/{i915, xe}: move opregion/dram/bw init to intel_display_driver_probe_noirq()
` [PATCH 4/6] drm/xe/display: change order of intel_display_driver_remove_{nogem, noirq}() calls
` [PATCH 5/6] drm/{i915, xe}: move opregion cleanup to intel_display_driver_remove_nogem()
` [PATCH 6/6] drm/{i915, xe}: move intel_hpd_cancel_work() to intel_display_driver_remove_noirq()
` ✓ i915.CI.BAT: success for drm/{i915, xe}: display probe/remove cleanup and unification
` ✓ i915.CI.Full: "
[PATCH v8 0/7] Vswing / Pre-emphasis Override
2026-06-16 3:41 UTC (10+ messages)
` [PATCH v8 1/7] drm/i915/bios: search for VBT #57 by default
` [PATCH v8 2/7] drm/i915/bios: store VBT #57's metadata in intel_vbt_data
` [PATCH v8 3/7] drm/i915/bios: print VS/PE-O port info
` [PATCH v8 4/7] drm/i915/bios: de/allocate VS/PE-O buffer for each port
` [PATCH v8 5/7] drm/i915: override Snps's VS/PE when requested
` [PATCH v8 6/7] drm/i915: override Combo's "
` [PATCH v8 7/7] drm/i915/bios: remove VS/PE-O warning
` ✓ i915.CI.BAT: success for Vswing / Pre-emphasis Override (rev3)
` ✓ i915.CI.Full: "
[PATCH 0/6] drm/{i915, xe}/panic: drop dependency on struct intel_framebuffer
2026-06-15 22:07 UTC (4+ messages)
` ✗ i915.CI.BAT: failure for drm/{i915, xe}/panic: drop dependency on struct intel_framebuffer (rev2)
` ✓ i915.CI.BAT: success for drm/{i915, xe}/panic: drop dependency on struct intel_framebuffer (rev3)
` ✓ i915.CI.Full: "
[PATCH 1/3] drm/i915/dsi: Program TRANS_HSYNC register for dual-link command mode
2026-06-15 17:20 UTC (2+ messages)
[PATCH] drm/i915/psr: Force fastset on debugfs write for each connector supporting PSR
2026-06-15 15:20 UTC (2+ messages)
[PATCH v7 0/8] Vswing / Pre-emphasis Override
2026-06-15 14:33 UTC (5+ messages)
` [PATCH v7 5/8] drm/i915: override Snps's VS/PE when requested
[PATCH] drm/i915/dsi: fix i2c adapter reference leak in i2c_adapter_lookup()
2026-06-15 14:24 UTC (2+ messages)
` ✗ LGCI.VerificationFailed: failure for "
[PATCH] [RFC] drm/i915/display: Fix PPC-granularity and limit 2nd scaler to 1:1
2026-06-15 14:13 UTC (3+ messages)
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