From: Sebastian Brzezinka <sebastian.brzezinka@intel.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: <intel-gfx@lists.freedesktop.org>, <andi.shyti@linux.intel.com>,
<vidya.srinivas@intel.com>, <matthew.d.roper@intel.com>
Subject: Re: [RFC PATCH] Revert "drm/i915: Disable compression tricks on JSL"
Date: Wed, 5 Mar 2025 17:00:26 +0000 [thread overview]
Message-ID: <D88HRP898QST.23MJT5TUM1HFR@intel.com> (raw)
In-Reply-To: <Z8htKL3L5ICwXzNb@intel.com>
Hi Ville
On Wed Mar 5, 2025 at 3:26 PM UTC, Ville Syrjälä wrote:
> On Wed, Mar 05, 2025 at 02:49:46PM +0000, Sebastian Brzezinka wrote:
>> This reverts commit 0ddae025ab6cefa9aba757da3cd1d27908d70b0e.
>>
>> According to bspec 14181, CACHE_MODE_0 is a register that's under userspace
>> control, and DISABLE_REPACKING_FOR_COMPRESSION workaround should be already
>> in all recent Mesa releases. So, there is no need to include it in kernel.
>
> igt doesn't have it.
>
>>
>> Also, this workaround·sporadically fails to load:
>> ```
>> ERROR GT0: engine workaround lost on application! (reg[7000]=0x0,
>> relevant bits were 0x0 vs expected 0x8000)
>> ```
>
> If it somehow fails to load from the kernel why would it
> work from userspace?
>
> Hmm, apparently CACHE_MODE_0 needs the mcr steering stuff.
> Does that fix the verification fail?
Thanks for sugestion. Right now I think that I try to move this wa to
icl_ctx_workarounds_init as both Mat and Chriss notice that register
is a part of the context.
--
Best regards,
Sebastian
next prev parent reply other threads:[~2025-03-05 17:00 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-05 14:49 [RFC PATCH] Revert "drm/i915: Disable compression tricks on JSL" Sebastian Brzezinka
2025-03-05 15:03 ` Sebastian Brzezinka
2025-03-05 15:26 ` Ville Syrjälä
2025-03-05 17:00 ` Sebastian Brzezinka [this message]
2025-03-06 12:52 ` Ville Syrjälä
2025-03-05 19:16 ` ✓ i915.CI.BAT: success for " Patchwork
2025-03-05 21:41 ` ✗ i915.CI.Full: failure " Patchwork
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