From: Andi Shyti <andi.shyti@intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 6/6] drm/i915/gt: Remove timeslice suppression
Date: Wed, 6 Jan 2021 02:07:40 +0200 [thread overview]
Message-ID: <X/T/THXWRdT6hs5N@intel.intel> (raw)
In-Reply-To: <20210104115145.24460-6-chris@chris-wilson.co.uk>
Hi Chris,
On Mon, Jan 04, 2021 at 11:51:45AM +0000, Chris Wilson wrote:
> In the next patch, we remove the strict priority system and continuously
next patch?
[...]
> -static bool
> -timeslice_expired(const struct intel_engine_execlists *el,
> - const struct i915_request *rq)
> +static bool needs_timeslice(const struct intel_engine_cs *engine,
> + const struct i915_request *rq)
> {
> - return timer_expired(&el->timer) || timeslice_yield(el, rq);
> -}
> + if (!intel_engine_has_timeslices(engine))
> + return false;
>
> -static int
> -switch_prio(struct intel_engine_cs *engine, const struct i915_request *rq)
> -{
> - if (list_is_last(&rq->sched.link, &engine->active.requests))
> - return engine->execlists.queue_priority_hint;
> + /* If not currently active, or about to switch, wait for next event */
> + if (!rq || __i915_request_is_complete(rq))
> + return false;
>
> - return rq_prio(list_next_entry(rq, sched.link));
> -}
> + /* We do not need to start the timeslice until after the ACK */
> + if (READ_ONCE(engine->execlists.pending[0]))
> + return false;
>
> -static inline unsigned long
> -timeslice(const struct intel_engine_cs *engine)
> -{
> - return READ_ONCE(engine->props.timeslice_duration_ms);
> + /* If ELSP[1] is occupied, always check to see if worth slicing */
> + if (!list_is_last_rcu(&rq->sched.link, &engine->active.requests))
> + return true;
> +
> + /* Otherwise, ELSP[0] is by itself, but may be waiting in the queue */
> + if (!RB_EMPTY_ROOT(&engine->execlists.queue.rb_root))
> + return true;
> +
> + return !RB_EMPTY_ROOT(&engine->execlists.virtual.rb_root);
> }
the above diff is quite unreadable and besides the patch does not
apply on the latest drm-tip.
In order to have a better review, I would suggest either one of
the following:
- use a different diff algorithm for generating the patch
- you rebase everything on top of the latest drm-tip so that I
can apply and check
- give me a branch so that I can checkout that branch and review
it from there.
Thanks,
Andi
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next prev parent reply other threads:[~2021-01-06 0:07 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-04 11:51 [Intel-gfx] [PATCH 1/6] drm/i915/selftests: Set error returns Chris Wilson
2021-01-04 11:51 ` [Intel-gfx] [PATCH 2/6] drm/i915: Set rawclk earlier during mmio probe Chris Wilson
2021-01-05 1:53 ` Andi Shyti
2021-01-04 11:51 ` [Intel-gfx] [PATCH 3/6] drm/i915/gt: Allow failed resets without assertion Chris Wilson
2021-01-05 1:55 ` Andi Shyti
2021-01-04 11:51 ` [Intel-gfx] [PATCH 4/6] drm/i915/gt: Check the virtual still matches upon locking Chris Wilson
2021-01-05 1:55 ` Andi Shyti
2021-01-04 11:51 ` [Intel-gfx] [PATCH 5/6] drm/i915/gt: Restore ce->signal flush before releasing virtual engine Chris Wilson
2021-01-05 1:57 ` Andi Shyti
2021-01-04 11:51 ` [Intel-gfx] [PATCH 6/6] drm/i915/gt: Remove timeslice suppression Chris Wilson
2021-01-06 0:07 ` Andi Shyti [this message]
2021-01-06 0:27 ` Chris Wilson
2021-01-06 0:29 ` [Intel-gfx] [PATCH] " Chris Wilson
2021-01-04 12:35 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] drm/i915/selftests: Set error returns Patchwork
2021-01-04 13:05 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-01-04 15:04 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-01-05 1:53 ` [Intel-gfx] [PATCH 1/6] " Andi Shyti
2021-01-06 1:07 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] drm/i915/selftests: Set error returns (rev2) Patchwork
2021-01-06 1:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-01-06 3:49 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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