Re: [Intel-gfx] [PULL] topic/dp-hdmi-2.1-pcon for drm-misc-next

[Daniel Vetter <daniel@ffwll.ch>]

On Wed, Dec 23, 2020 at 10:14:58AM +0200, Jani Nikula wrote:
> 
> Hi Maarten, Maxime, and Thomas -
> 
> Here's the DP-HDMI2.1 PCON support topic pull consisting of the series
> [1]. The series is split roughly 50-50 between drm helpers and i915, so
> a topic branch seemed to be the right way to go.
> 
> I'll also pull this to drm-intel-next once you've merged to
> drm-misc-next.

I didn't see this merged into drm-misc-next, so pulled into drm-next. I'm
processing an entire batch of pulls, I'll ping you on irc when it's all
ready for backmerging.

Cheers, Daniel

> 
> BR,
> Jani.
> 
> 
> [1] https://patchwork.freedesktop.org/series/82098/
> 
> 
> topic/dp-hdmi-2.1-pcon-2020-12-23:
> Add support for DP-HDMI2.1 PCON
> 
> From the series cover letter:
> 
> This patch series attempts to add support for a DP-HDMI2.1 Protocol
> Convertor. The VESA spec for the HDMI2.1 PCON are proposed in Errata
> E5 to DisplayPort_v2.0:
> https://vesa.org/join-vesamemberships/member-downloads/?action=stamp&fileid=42299
> The details are mentioned in:
> VESA DP-to-HDMI PCON Specification Standalone Document
> https://groups.vesa.org/wg/DP/document/15651
> 
> This series starts with adding support for FRL (Fixed Rate Link)
> Training between the PCON and HDMI2.1 sink.
> As per HDMI2.1 specification, a new data-channel or lane is added in
> FRL mode, by repurposing the TMDS clock Channel. Through FRL, higher
> bit-rate can be supported, ie. up to 12 Gbps/lane (48 Gbps over 4
> lanes).
> 
> With these patches, the HDMI2.1 PCON can be configured to achieve FRL
> training based on the maximum FRL rate supported by the panel, source
> and the PCON.
> The approach is to add the support for FRL training between PCON and
> HDMI2.1 sink and gradually add other blocks for supporting higher
> resolutions and other HDMI2.1 features, that can be supported by pcon
> for the sources that do not natively support HDMI2.1.
> 
> This is done before the DP Link training between the source and PCON
> is started. In case of FRL training is not achieved, the PCON will
> work in the regular TMDS mode, without HDMI2.1 feature support.
> Any interruption in FRL training between the PCON and HDMI2.1 sink is
> notified through IRQ_HPD. On receiving the IRQ_HPD the concerned DPCD
> registers are read and FRL training is re-attempted.
> 
> Currently, we have tested the FRL training and are able to enable 4K
> display with TGL Platform + Realtek PCON RTD2173 with HDMI2.1 supporting
> panel.
> 
> The following changes since commit b3bf99daaee96a141536ce5c60a0d6dba6ec1d23:
> 
>   drm/i915/display: Defer initial modeset until after GGTT is initialised (2020-11-26 11:01:52 +0000)
> 
> are available in the Git repository at:
> 
>   git://anongit.freedesktop.org/drm/drm-intel tags/topic/dp-hdmi-2.1-pcon-2020-12-23
> 
> for you to fetch changes up to 522508b665df3bbfdf40381d4e61777844b1703f:
> 
>   drm/i915/display: Let PCON convert from RGB to YCbCr if it can (2020-12-22 17:59:07 +0200)
> 
> ----------------------------------------------------------------
> Add support for DP-HDMI2.1 PCON
> 
> From the series cover letter:
> 
> This patch series attempts to add support for a DP-HDMI2.1 Protocol
> Convertor. The VESA spec for the HDMI2.1 PCON are proposed in Errata
> E5 to DisplayPort_v2.0:
> https://vesa.org/join-vesamemberships/member-downloads/?action=stamp&fileid=42299
> The details are mentioned in:
> VESA DP-to-HDMI PCON Specification Standalone Document
> https://groups.vesa.org/wg/DP/document/15651
> 
> This series starts with adding support for FRL (Fixed Rate Link)
> Training between the PCON and HDMI2.1 sink.
> As per HDMI2.1 specification, a new data-channel or lane is added in
> FRL mode, by repurposing the TMDS clock Channel. Through FRL, higher
> bit-rate can be supported, ie. up to 12 Gbps/lane (48 Gbps over 4
> lanes).
> 
> With these patches, the HDMI2.1 PCON can be configured to achieve FRL
> training based on the maximum FRL rate supported by the panel, source
> and the PCON.
> The approach is to add the support for FRL training between PCON and
> HDMI2.1 sink and gradually add other blocks for supporting higher
> resolutions and other HDMI2.1 features, that can be supported by pcon
> for the sources that do not natively support HDMI2.1.
> 
> This is done before the DP Link training between the source and PCON
> is started. In case of FRL training is not achieved, the PCON will
> work in the regular TMDS mode, without HDMI2.1 feature support.
> Any interruption in FRL training between the PCON and HDMI2.1 sink is
> notified through IRQ_HPD. On receiving the IRQ_HPD the concerned DPCD
> registers are read and FRL training is re-attempted.
> 
> Currently, we have tested the FRL training and are able to enable 4K
> display with TGL Platform + Realtek PCON RTD2173 with HDMI2.1 supporting
> panel.
> 
> ----------------------------------------------------------------
> Ankit Nautiyal (11):
>       drm/edid: Parse DSC1.2 cap fields from HFVSDB block
>       drm/dp_helper: Add Helpers for FRL Link Training support for DP-HDMI2.1 PCON
>       drm/dp_helper: Add support for Configuring DSC for HDMI2.1 Pcon
>       drm/dp_helper: Add helpers to configure PCONs RGB-YCbCr Conversion
>       drm/i915: Capture max frl rate for PCON in dfp cap structure
>       drm/i915: Add support for starting FRL training for HDMI2.1 via PCON
>       drm/i915: Check for FRL training before DP Link training
>       drm/i915: Read DSC capabilities of the HDMI2.1 PCON encoder
>       drm/i915: Add helper functions for calculating DSC parameters for HDMI2.1
>       drm/i915/display: Configure PCON for DSC1.1 to DSC1.2 encoding
>       drm/i915/display: Let PCON convert from RGB to YCbCr if it can
> 
> Swati Sharma (4):
>       drm/edid: Add additional HFVSDB fields for HDMI2.1
>       drm/edid: Parse MAX_FRL field from HFVSDB block
>       drm/dp_helper: Add support for link failure detection
>       drm/i915: Add support for enabling link status and recovery
> 
>  drivers/gpu/drm/drm_dp_helper.c                    | 566 +++++++++++++++++++++
>  drivers/gpu/drm/drm_edid.c                         | 103 ++++
>  drivers/gpu/drm/i915/display/intel_ddi.c           |   6 +-
>  drivers/gpu/drm/i915/display/intel_display_types.h |  10 +
>  drivers/gpu/drm/i915/display/intel_dp.c            | 440 +++++++++++++++-
>  drivers/gpu/drm/i915/display/intel_dp.h            |   7 +-
>  drivers/gpu/drm/i915/display/intel_hdmi.c          | 233 +++++++++
>  drivers/gpu/drm/i915/display/intel_hdmi.h          |   7 +
>  include/drm/drm_connector.h                        |  49 ++
>  include/drm/drm_dp_helper.h                        | 218 ++++++++
>  include/drm/drm_edid.h                             |  30 ++
>  11 files changed, 1650 insertions(+), 19 deletions(-)
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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