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From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
To: Matt Roper <matthew.d.roper@intel.com>,
	<intel-gfx@lists.freedesktop.org>
Cc: dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v3 02/14] drm/i915/xehp: Create separate reg definitions for new MCR registers
Date: Mon, 17 Oct 2022 22:19:45 +0530	[thread overview]
Message-ID: <Y02HqcnTRESLHL26@bala-ubuntu> (raw)
In-Reply-To: <20221014230239.1023689-3-matthew.d.roper@intel.com>

On 14.10.2022 16:02, Matt Roper wrote:
> Starting in Xe_HP, several registers our driver works with have been
> converted from singleton registers into replicated registers with
> multicast behavior.  Although the registers are still located at the
> same MMIO offsets as on previous platforms, let's duplicate the register
> definitions in preparation for upcoming patches that will handle
> multicast registers in a special manner.
> 
> The registers that are now replicated on Xe_HP are:
>  * PAT_INDEX (mslice replication)
>  * FF_MODE2 (gslice replication)
>  * COMMON_SLICE_CHICKEN3 (gslice replication)
>  * SLICE_COMMON_ECO_CHICKEN1 (gslice replication)
>  * SLICE_UNIT_LEVEL_CLKGATE (gslice replication)
>  * LNCFCMOCS (lncf replication)
> 
> Note that there are a couple places in selftest_mocs.c where the
> gen9 version of LNCFCMOCS is still used without regards for which
> platform we're on.  Those cases are just doing an offset lookup and not
> issuing any CPU reads/writes of the register, so the potentially
> multicast nature of the register doesn't come into play.
> 
> v2:
>  - Add commit message note about the unconditional GEN9_LNCFCMOCS usage
>    in selftest_mocs.  (Bala)
>  - Include some additional TLB registers.
> 
> Bspec: 66534
> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_ggtt.c        |  4 ++--
>  drivers/gpu/drm/i915/gt/intel_gt.c          | 18 ++++++++++++--
>  drivers/gpu/drm/i915/gt/intel_gt_regs.h     | 26 +++++++++++++++------
>  drivers/gpu/drm/i915/gt/intel_gtt.c         | 22 ++++++++++++++---
>  drivers/gpu/drm/i915/gt/intel_gtt.h         |  2 +-
>  drivers/gpu/drm/i915/gt/intel_mocs.c        |  5 +++-
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +++++++++----------
>  drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c  |  7 ++++--
>  8 files changed, 78 insertions(+), 30 deletions(-)

Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

Regards,
Bala

  reply	other threads:[~2022-10-17 16:50 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-14 23:02 [Intel-gfx] [PATCH v3 00/14] Explicit MCR handling and MTL steering Matt Roper
2022-10-14 23:02 ` [Intel-gfx] [PATCH v3 01/14] drm/i915/gen8: Create separate reg definitions for new MCR registers Matt Roper
2022-10-17 16:49   ` Balasubramani Vivekanandan
2022-10-14 23:02 ` [Intel-gfx] [PATCH v3 02/14] drm/i915/xehp: " Matt Roper
2022-10-17 16:49   ` Balasubramani Vivekanandan [this message]
2022-10-14 23:02 ` [Intel-gfx] [PATCH v3 03/14] drm/i915/gt: Drop a few unused register definitions Matt Roper
2022-10-17 16:50   ` Balasubramani Vivekanandan
2022-10-14 23:02 ` [Intel-gfx] [PATCH v3 04/14] drm/i915/gt: Correct prefix on a few registers Matt Roper
2022-10-17 16:51   ` Balasubramani Vivekanandan
2022-10-14 23:02 ` [Intel-gfx] [PATCH v3 05/14] drm/i915/gt: Add intel_gt_mcr_multicast_rmw() operation Matt Roper
2022-10-17 16:51   ` Balasubramani Vivekanandan
2022-10-14 23:02 ` [Intel-gfx] [PATCH v3 06/14] drm/i915/xehp: Check for faults on primary GAM Matt Roper
2022-10-17 16:52   ` Balasubramani Vivekanandan
2022-10-14 23:02 ` [Intel-gfx] [PATCH v3 07/14] drm/i915/gt: Add intel_gt_mcr_wait_for_reg_fw() Matt Roper
2022-10-17 16:52   ` Balasubramani Vivekanandan
2022-10-14 23:02 ` [Intel-gfx] [PATCH v3 08/14] drm/i915: Define MCR registers explicitly Matt Roper
2022-10-17 16:53   ` Balasubramani Vivekanandan
2022-10-14 23:02 ` [Intel-gfx] [PATCH v3 09/14] drm/i915/gt: Always use MCR functions on multicast registers Matt Roper
2022-10-17 16:53   ` Balasubramani Vivekanandan
2022-10-14 23:02 ` [Intel-gfx] [PATCH v3 10/14] drm/i915/guc: Handle save/restore of MCR registers explicitly Matt Roper
2022-10-17 16:54   ` Balasubramani Vivekanandan
2022-10-14 23:02 ` [Intel-gfx] [PATCH v3 11/14] drm/i915/gt: Add MCR-specific workaround initializers Matt Roper
2022-10-17 16:54   ` Balasubramani Vivekanandan
2022-10-14 23:02 ` [Intel-gfx] [PATCH v3 12/14] drm/i915: Define multicast registers as a new type Matt Roper
2022-10-17 16:59   ` Balasubramani Vivekanandan
2022-10-14 23:02 ` [Intel-gfx] [PATCH v3 13/14] drm/i915/xelpg: Add multicast steering Matt Roper
2022-10-17 17:01   ` Balasubramani Vivekanandan
2022-10-14 23:02 ` [Intel-gfx] [PATCH v3 14/14] drm/i915/xelpmp: Add multicast steering for media GT Matt Roper
2022-10-17 17:02   ` Balasubramani Vivekanandan
2022-10-14 23:20 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Explicit MCR handling and MTL steering (rev4) Patchwork
2022-10-14 23:21 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-10-14 23:40 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-10-15  1:03 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-10-17 16:17   ` Matt Roper
2022-10-17 17:40     ` Matt Roper
2022-10-17 18:10     ` Vudum, Lakshminarayana

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