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From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
To: "Dixit, Ashutosh" <ashutosh.dixit@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v3 04/16] drm/i915/perf: Determine gen12 oa ctx offset at runtime
Date: Tue, 11 Oct 2022 09:36:08 -0700	[thread overview]
Message-ID: <Y0WbeIQMzTZeOcjA@unerlige-ril> (raw)
In-Reply-To: <87tu4b1adz.wl-ashutosh.dixit@intel.com>

On Mon, Oct 10, 2022 at 05:17:44PM -0700, Dixit, Ashutosh wrote:
>On Mon, 10 Oct 2022 11:14:22 -0700, Umesh Nerlige Ramappa wrote:
>
>Hi Umesh,
>
>> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
>> index cd57b5836386..b292aa39633e 100644
>> --- a/drivers/gpu/drm/i915/i915_perf.c
>> +++ b/drivers/gpu/drm/i915/i915_perf.c
>> @@ -1358,6 +1358,68 @@ static int gen12_get_render_context_id(struct i915_perf_stream *stream)
>>	return 0;
>>  }
>>
>> +#define valid_oactxctrl_offset(x) ((x) && (x) != U32_MAX)
>> +static bool oa_find_reg_in_lri(u32 *state, u32 reg, u32 *offset, u32 end)
>> +{
>> +	u32 idx = *offset;
>> +	u32 len = min(MI_LRI_LEN(state[idx]) + idx, end);
>> +	bool found = false;
>
>My recommendation would be to put something like this here:
>
>	if (MI_LRI_LEN(state[idx]) & 0x1)
>		drm_warn("MI_LRI instruction with odd length\n");
>
>Because we expect the MI_LRI length to even and I am not sure what is in
>the context image. But maybe not needed?

will add.

>
>> @@ -2436,15 +2514,18 @@ static int gen12_configure_oar_context(struct i915_perf_stream *stream,
>>		},
>>	};
>>
>> -	/* Modify the context image of pinned context with regs_context*/
>> -	err = intel_context_lock_pinned(ce);
>> -	if (err)
>> -		return err;
>> +	/* Modify the context image of pinned context with regs_context */
>> +	if (valid_oactxctrl_offset(offset)) {
>
>As I said before, this check is not needed, if we didn't have valid a
>offset we should return error from oa_get_render_ctx_id. For if we have
>this check and offset is not valid, can we skip this code and will things
>still work? Or do we need to return an error from
>gen12_configure_oar_context?

I missed that from the previous comments. Will add.

>
>> +		err = intel_context_lock_pinned(ce);
>> +		if (err)
>> +			return err;
>>
>> -	err = gen8_modify_context(ce, regs_context, ARRAY_SIZE(regs_context));
>> -	intel_context_unlock_pinned(ce);
>> -	if (err)
>> -		return err;
>> +		err = gen8_modify_context(ce, regs_context,
>> +					  ARRAY_SIZE(regs_context));
>> +		intel_context_unlock_pinned(ce);
>> +		if (err)
>> +			return err;
>> +	}
>
>With the if statement removed or handled otherwise, this is:
>
>Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

  reply	other threads:[~2022-10-11 16:49 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-10 18:14 [Intel-gfx] [PATCH v3 00/16] Add DG2 OA support Umesh Nerlige Ramappa
2022-10-10 18:14 ` [Intel-gfx] [PATCH v3 01/16] drm/i915/perf: Fix OA filtering logic for GuC mode Umesh Nerlige Ramappa
2022-10-10 18:14 ` [Intel-gfx] [PATCH v3 02/16] drm/i915/perf: Add 32-bit OAG and OAR formats for DG2 Umesh Nerlige Ramappa
2022-10-10 18:14 ` [Intel-gfx] [PATCH v3 03/16] drm/i915/perf: Fix noa wait predication " Umesh Nerlige Ramappa
2022-10-10 18:14 ` [Intel-gfx] [PATCH v3 04/16] drm/i915/perf: Determine gen12 oa ctx offset at runtime Umesh Nerlige Ramappa
2022-10-11  0:17   ` Dixit, Ashutosh
2022-10-11 16:36     ` Umesh Nerlige Ramappa [this message]
2022-10-11 17:47   ` Jani Nikula
2022-10-11 18:19     ` Umesh Nerlige Ramappa
2022-10-12 16:12       ` Jani Nikula
2022-10-10 18:14 ` [Intel-gfx] [PATCH v3 05/16] drm/i915/perf: Enable bytes per clock reporting in OA Umesh Nerlige Ramappa
2022-10-10 18:14 ` [Intel-gfx] [PATCH v3 06/16] drm/i915/perf: Simply use stream->ctx Umesh Nerlige Ramappa
2022-10-10 18:14 ` [Intel-gfx] [PATCH v3 07/16] drm/i915/perf: Move gt-specific data from i915->perf to gt->perf Umesh Nerlige Ramappa
2022-10-10 18:14 ` [Intel-gfx] [PATCH v3 08/16] drm/i915/perf: Replace gt->perf.lock with stream->lock for file ops Umesh Nerlige Ramappa
2022-10-10 18:14 ` [Intel-gfx] [PATCH v3 09/16] drm/i915/perf: Use gt-specific ggtt for OA and noa-wait buffers Umesh Nerlige Ramappa
2022-10-10 18:14 ` [Intel-gfx] [PATCH v3 10/16] drm/i915/perf: Store a pointer to oa_format in oa_buffer Umesh Nerlige Ramappa
2022-10-10 18:14 ` [Intel-gfx] [PATCH v3 11/16] drm/i915/perf: Add Wa_1508761755:dg2 Umesh Nerlige Ramappa
2022-10-10 18:14 ` [Intel-gfx] [PATCH v3 12/16] drm/i915/perf: Apply Wa_18013179988 Umesh Nerlige Ramappa
2022-10-10 18:14 ` [Intel-gfx] [PATCH v3 13/16] drm/i915/perf: Save/restore EU flex counters across reset Umesh Nerlige Ramappa
2022-10-10 18:14 ` [Intel-gfx] [PATCH v3 14/16] drm/i915/guc: Support OA when Wa_16011777198 is enabled Umesh Nerlige Ramappa
2022-10-10 18:14 ` [Intel-gfx] [PATCH v3 15/16] drm/i915/perf: complete programming whitelisting for XEHPSDV Umesh Nerlige Ramappa
2022-10-11  0:34   ` Dixit, Ashutosh
2022-10-11 16:38     ` Umesh Nerlige Ramappa
2022-10-10 18:14 ` [Intel-gfx] [PATCH v3 16/16] drm/i915/perf: Enable OA for DG2 Umesh Nerlige Ramappa
2022-10-11  0:35   ` Dixit, Ashutosh
2022-10-10 22:19 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DG2 OA support (rev5) Patchwork
2022-10-10 22:19 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork

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