Re: [Intel-gfx] [PATCH 4/5] drm/i915/mtl: add GSC CS reset support

[Matt Roper <matthew.d.roper@intel.com>]

On Thu, Oct 27, 2022 at 03:15:53PM -0700, Daniele Ceraolo Spurio wrote:
> The GSC CS has its own dedicated bit in the GDRST register.
> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>

Bspec: 52549
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_engine_cs.c | 1 +
>  drivers/gpu/drm/i915/gt/intel_gt_regs.h   | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index e0fbfac03979..f63829abf66c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -423,6 +423,7 @@ static u32 get_reset_domain(u8 ver, enum intel_engine_id id)
>  			[CCS1]  = GEN11_GRDOM_RENDER,
>  			[CCS2]  = GEN11_GRDOM_RENDER,
>  			[CCS3]  = GEN11_GRDOM_RENDER,
> +			[GSC0]  = GEN12_GRDOM_GSC,
>  		};
>  		GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) ||
>  			   !engine_reset_domains[id]);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 23844ba7e824..16cf90306085 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -640,6 +640,7 @@
>  #define   XEHPC_GRDOM_BLT3			REG_BIT(26)
>  #define   XEHPC_GRDOM_BLT2			REG_BIT(25)
>  #define   XEHPC_GRDOM_BLT1			REG_BIT(24)
> +#define   GEN12_GRDOM_GSC			REG_BIT(21)
>  #define   GEN11_GRDOM_SFC3			REG_BIT(20)
>  #define   GEN11_GRDOM_SFC2			REG_BIT(19)
>  #define   GEN11_GRDOM_SFC1			REG_BIT(18)
> -- 
> 2.37.3
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation