From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: intel-gfx@lists.freedesktop.org,
Jonathan Cavitt <jonathan.cavitt@intel.com>,
dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 5/6] drm/i915/gsc: Disable GSC engine and power well if FW is not selected
Date: Tue, 22 Nov 2022 15:52:22 -0500 [thread overview]
Message-ID: <Y302hgNHNFN0oElo@intel.com> (raw)
In-Reply-To: <20221121231617.1110329-6-daniele.ceraolospurio@intel.com>
On Mon, Nov 21, 2022 at 03:16:16PM -0800, Daniele Ceraolo Spurio wrote:
> From: Jonathan Cavitt <jonathan.cavitt@intel.com>
>
> The GSC CS is only used for communicating with the GSC FW, so no need to
> initialize it if we're not going to use the FW. If we're not using
> neither the engine nor the microcontoller, then we can also disable the
> power well.
>
> IMPORTANT: lack of GSC FW breaks media C6 due to opposing requirements
> between CS setup and forcewake idleness. See in-code comment for detail.
>
> Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: John C Harrison <John.C.Harrison@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 18 ++++++++++++++++++
> drivers/gpu/drm/i915/intel_uncore.c | 3 +++
> 2 files changed, 21 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index c33e0d72d670..99c4b866addd 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -894,6 +894,24 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
> engine_mask_apply_compute_fuses(gt);
> engine_mask_apply_copy_fuses(gt);
>
> + /*
> + * The only use of the GSC CS is to load and communicate with the GSC
> + * FW, so we have no use for it if we don't have the FW.
> + *
> + * IMPORTANT: in cases where we don't have the GSC FW, we have a
> + * catch-22 situation that breaks media C6 due to 2 requirements:
> + * 1) once turned on, the GSC power well will not go to sleep unless the
> + * GSC FW is loaded.
> + * 2) to enable idling (which is required for media C6) we need to
> + * initialize the IDLE_MSG register for the GSC CS and do at least 1
> + * submission, which will wake up the GSC power well.
> + */
> + if (__HAS_ENGINE(info->engine_mask, GSC0) && !intel_uc_wants_gsc_uc(>->uc)) {
> + drm_notice(>->i915->drm,
> + "No GSC FW selected, disabling GSC CS and media C6\n");
> + info->engine_mask &= ~BIT(GSC0);
> + }
> +
> return info->engine_mask;
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index c1befa33ff59..e63d957b59eb 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -2701,6 +2701,9 @@ void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
> if (fw_domains & BIT(domain_id))
> fw_domain_fini(uncore, domain_id);
> }
> +
> + if ((fw_domains & BIT(FW_DOMAIN_ID_GSC)) && !HAS_ENGINE(gt, GSC0))
> + fw_domain_fini(uncore, FW_DOMAIN_ID_GSC);
On a quick glace I was asking "why do you need this since it doesn't have the gsc0?
Then I remember that fw_domain got initialized and it will be skipped, right?
Then I though about at least have a comment here, but finally I got myself wondering
why we don't do this already in the if above, while we are cleaning the engine mask?
> }
>
> static void driver_flr(struct intel_uncore *uncore)
> --
> 2.37.3
>
next prev parent reply other threads:[~2022-11-22 20:52 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-21 23:16 [Intel-gfx] [PATCH 0/6] drm/i915: Add support for GSC FW loading Daniele Ceraolo Spurio
2022-11-21 23:16 ` [Intel-gfx] [PATCH 1/6] drm/i915/uc: Introduce GSC FW Daniele Ceraolo Spurio
2022-11-22 9:03 ` Jani Nikula
2022-11-22 19:42 ` Ceraolo Spurio, Daniele
2022-11-22 20:11 ` Jani Nikula
2022-11-29 23:48 ` Teres Alexis, Alan Previn
2022-11-30 17:08 ` Ceraolo Spurio, Daniele
2022-11-21 23:16 ` [Intel-gfx] [PATCH 2/6] drm/i915/gsc: Skip the version check when fetching the " Daniele Ceraolo Spurio
2022-11-22 18:53 ` Rodrigo Vivi
2022-11-21 23:16 ` [Intel-gfx] [PATCH 3/6] drm/i915/gsc: GSC firmware loading Daniele Ceraolo Spurio
2022-11-22 19:01 ` Rodrigo Vivi
2022-11-22 19:39 ` Ceraolo Spurio, Daniele
2022-11-22 20:58 ` Rodrigo Vivi
2022-12-01 22:00 ` Teres Alexis, Alan Previn
2022-11-21 23:16 ` [Intel-gfx] [PATCH 4/6] drm/i915/gsc: Do a driver-FLR on unload if GSC was loaded Daniele Ceraolo Spurio
2022-11-22 0:17 ` Ceraolo Spurio, Daniele
2022-11-22 20:46 ` Rodrigo Vivi
2022-11-22 22:50 ` Ceraolo Spurio, Daniele
2022-11-23 18:32 ` Rodrigo Vivi
2022-12-01 22:40 ` Teres Alexis, Alan Previn
2022-12-01 22:52 ` Ceraolo Spurio, Daniele
2022-11-21 23:16 ` [Intel-gfx] [PATCH 5/6] drm/i915/gsc: Disable GSC engine and power well if FW is not selected Daniele Ceraolo Spurio
2022-11-22 20:52 ` Rodrigo Vivi [this message]
2022-11-22 22:58 ` Ceraolo Spurio, Daniele
2022-11-23 18:34 ` Rodrigo Vivi
2022-11-21 23:16 ` [Intel-gfx] [PATCH 6/6] drm/i915/mtl: MTL has one GSC CS on the media GT Daniele Ceraolo Spurio
2022-11-22 20:52 ` Rodrigo Vivi
2022-11-21 23:42 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add support for GSC FW loading Patchwork
2022-11-21 23:42 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-11-22 0:08 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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