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From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915: Implement workaround for DP2 UHBR bandwidth check
Date: Tue, 10 Jan 2023 14:12:17 -0500	[thread overview]
Message-ID: <Y724kUKsBH34H51P@intel.com> (raw)
In-Reply-To: <20230110123338.20196-1-stanislav.lisovskiy@intel.com>

On Tue, Jan 10, 2023 at 02:33:38PM +0200, Stanislav Lisovskiy wrote:
> According to spec, we should check if output_bpp * pixel_rate is less
> than DDI clock * 72, if UHBR is used.
> 
> HSDES: 1406899791
> BSPEC: 49259
> 
> v2: - Removed wrong comment(Rodrigo Vivi)
>     - Added HSDES to the commit msg(Rodrigo Vivi)
>     - Moved UHBR check to the MST specific code

I'm afraid you forgot to remove the "workaround" from the patch subject.

> 
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp_mst.c | 15 ++++++++++++---
>  1 file changed, 12 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 8b0e4defa3f1..1f1f7f5f6501 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -339,10 +339,19 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
>  		ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
>  						  conn_state, &limits,
>  						  pipe_config->dp_m_n.tu, false);
> -	}
> +		if (ret < 0)
> +			return ret;
>  
> -	if (ret)
> -		return ret;
> +		if (intel_dp_is_uhbr(pipe_config)) {
> +			int output_bpp = pipe_config->dsc.compressed_bpp;
> +
> +			if (output_bpp * adjusted_mode->crtc_clock >=
> +			    pipe_config->port_clock * 72) {
> +				drm_dbg_kms(&dev_priv->drm, "DP2 UHBR check failed\n");

I'm wondering if I misunderstood your recent reply....  but I believe you told this
has nothing to do with DP2.0 so why we have DP2 in the msg still?

I believe that or:
1. We are sure this case is only happening on DP2.0 because it is impossible
2. or because we are adding a DP2.0 check
3. or we don't mention DP2.0

With the subject and the comment fixed:

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> +				return -EINVAL;
> +			}
> +		}
> +	}
>  
>  	ret = intel_dp_mst_update_slots(encoder, pipe_config, conn_state);
>  	if (ret)
> -- 
> 2.37.3
> 

  parent reply	other threads:[~2023-01-10 19:12 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-10 12:33 [Intel-gfx] [PATCH] drm/i915: Implement workaround for DP2 UHBR bandwidth check Stanislav Lisovskiy
2023-01-10 16:12 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Implement workaround for DP2 UHBR bandwidth check (rev2) Patchwork
2023-01-10 19:12 ` Rodrigo Vivi [this message]
2023-01-11  9:17   ` [Intel-gfx] [PATCH] drm/i915: Implement workaround for DP2 UHBR bandwidth check Lisovskiy, Stanislav
2023-01-10 21:20 ` [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Implement workaround for DP2 UHBR bandwidth check (rev2) Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2023-01-02 11:39 [Intel-gfx] [PATCH] drm/i915: Implement workaround for DP2 UHBR bandwidth check Stanislav Lisovskiy
2023-01-03 16:32 ` Rodrigo Vivi
2023-01-09 15:06   ` Lisovskiy, Stanislav

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