Re: [Intel-gfx] [RFC 2/2] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U

[Matt Roper <matthew.d.roper@intel.com>]

On Tue, Jan 10, 2023 at 11:06:14AM +0200, Jani Nikula wrote:
> On Sat, 07 Jan 2023, Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> wrote:
> > A new step of 480MHz has been added on SKUs that have a RPL-U
> > device id to support 120Hz displays more efficiently. Use a
> > new quirk to identify the machine for which this change needs
> > to be applied.
> >
> > BSpec: 55409
> >
> > Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_cdclk.c | 23 ++++++++++++++++++++++
> >  1 file changed, 23 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index 0c107a38f9d0..a437ac446871 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -1329,6 +1329,27 @@ static const struct intel_cdclk_vals adlp_cdclk_table[] = {
> >  	{}
> >  };
> >  
> > +static const struct intel_cdclk_vals rplu_cdclk_table[] = {
> > +	{ .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
> > +	{ .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
> > +	{ .refclk = 19200, .cdclk = 480000, .divider = 2, .ratio = 50 },
> > +	{ .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> > +	{ .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> > +
> > +	{ .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
> > +	{ .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
> > +	{ .refclk = 24000, .cdclk = 480000, .divider = 2, .ratio = 40 },
> > +	{ .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> > +	{ .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
> > +
> > +	{ .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
> > +	{ .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> > +	{ .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25 },
> > +	{ .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> > +	{ .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> > +	{}
> > +};
> > +
> >  static const struct intel_cdclk_vals dg2_cdclk_table[] = {
> >  	{ .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 },
> >  	{ .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 },
> > @@ -3353,6 +3374,8 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
> >  		/* Wa_22011320316:adl-p[a0] */
> >  		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> >  			dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
> 
> Are RPL-U A0-B0 going to enter this branch? Is this the right thing to
> do?

There's no such thing as a RPL A0/B0.  RPL continues the stepping
progression from ADL, and all RPL parts have E0 or newer display
steppings (bspec 55376).


Matt

> 
> BR,
> Jani.
> 
> 
> > +		else if (IS_ADLP_RPLU(dev_priv))
> > +			dev_priv->display.cdclk.table = rplu_cdclk_table;
> >  		else
> >  			dev_priv->display.cdclk.table = adlp_cdclk_table;
> >  	} else if (IS_ROCKETLAKE(dev_priv)) {
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation