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From: Andi Shyti <andi.shyti@linux.intel.com>
To: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Cc: paulo.r.zanoni@intel.com, jani.nikula@intel.com,
	intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
	thomas.hellstrom@intel.com, matthew.auld@intel.com,
	daniel.vetter@intel.com, christian.koenig@amd.com
Subject: Re: [Intel-gfx] [PATCH v10 20/23] drm/i915/vm_bind: Render VM_BIND documentation
Date: Thu, 2 Feb 2023 17:38:55 +0100	[thread overview]
Message-ID: <Y9vnHzZslHcKCZFi@ashyti-mobl2.lan> (raw)
In-Reply-To: <20230118071609.17572-21-niranjana.vishwanathapura@intel.com>

Hi Niranjana,

On Tue, Jan 17, 2023 at 11:16:06PM -0800, Niranjana Vishwanathapura wrote:
> Update i915 documentation to include VM_BIND changes
> and render all VM_BIND related documentation.
> 
> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>

looks good!

Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>

Andi

> ---
>  Documentation/gpu/i915.rst | 78 ++++++++++++++++++++++++++++----------
>  1 file changed, 59 insertions(+), 19 deletions(-)
> 
> diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
> index 60ea21734902..01429a8f0d6c 100644
> --- a/Documentation/gpu/i915.rst
> +++ b/Documentation/gpu/i915.rst
> @@ -283,15 +283,18 @@ An Intel GPU has multiple engines. There are several engine types.
>  
>  The Intel GPU family is a family of integrated GPU's using Unified
>  Memory Access. For having the GPU "do work", user space will feed the
> -GPU batch buffers via one of the ioctls `DRM_IOCTL_I915_GEM_EXECBUFFER2`
> -or `DRM_IOCTL_I915_GEM_EXECBUFFER2_WR`. Most such batchbuffers will
> -instruct the GPU to perform work (for example rendering) and that work
> -needs memory from which to read and memory to which to write. All memory
> -is encapsulated within GEM buffer objects (usually created with the ioctl
> -`DRM_IOCTL_I915_GEM_CREATE`). An ioctl providing a batchbuffer for the GPU
> -to create will also list all GEM buffer objects that the batchbuffer reads
> -and/or writes. For implementation details of memory management see
> -`GEM BO Management Implementation Details`_.
> +GPU batch buffers via one of the ioctls `DRM_IOCTL_I915_GEM_EXECBUFFER2`,
> +`DRM_IOCTL_I915_GEM_EXECBUFFER2_WR` or `DRM_IOCTL_I915_GEM_EXECBUFFER3`.
> +Most such batchbuffers will instruct the GPU to perform work (for example
> +rendering) and that work needs memory from which to read and memory to
> +which to write. All memory is encapsulated within GEM buffer objects
> +(usually created with the ioctl `DRM_IOCTL_I915_GEM_CREATE`). In vm_bind mode
> +(see `VM_BIND mode`_), the batch buffer and all the GEM buffer objects that
> +it reads and/or writes should be bound with vm_bind ioctl before submitting
> +the batch buffer to GPU. In legacy (non-VM_BIND) mode, an ioctl providing a
> +batchbuffer for the GPU to create will also list all GEM buffer objects that
> +the batchbuffer reads and/or writes. For implementation details of memory
> +management see `GEM BO Management Implementation Details`_.
>  
>  The i915 driver allows user space to create a context via the ioctl
>  `DRM_IOCTL_I915_GEM_CONTEXT_CREATE` which is identified by a 32-bit
> @@ -309,8 +312,9 @@ In addition to the ordering guarantees, the kernel will restore GPU
>  state via HW context when commands are issued to a context, this saves
>  user space the need to restore (most of atleast) the GPU state at the
>  start of each batchbuffer. The non-deprecated ioctls to submit batchbuffer
> -work can pass that ID (in the lower bits of drm_i915_gem_execbuffer2::rsvd1)
> -to identify what context to use with the command.
> +work can pass that ID (drm_i915_gem_execbuffer3::ctx_id, or in the lower
> +bits of drm_i915_gem_execbuffer2::rsvd1) to identify what context to use
> +with the command.
>  
>  The GPU has its own memory management and address space. The kernel
>  driver maintains the memory translation table for the GPU. For older
> @@ -318,14 +322,14 @@ GPUs (i.e. those before Gen8), there is a single global such translation
>  table, a global Graphics Translation Table (GTT). For newer generation
>  GPUs each context has its own translation table, called Per-Process
>  Graphics Translation Table (PPGTT). Of important note, is that although
> -PPGTT is named per-process it is actually per context. When user space
> -submits a batchbuffer, the kernel walks the list of GEM buffer objects
> -used by the batchbuffer and guarantees that not only is the memory of
> -each such GEM buffer object resident but it is also present in the
> -(PP)GTT. If the GEM buffer object is not yet placed in the (PP)GTT,
> -then it is given an address. Two consequences of this are: the kernel
> -needs to edit the batchbuffer submitted to write the correct value of
> -the GPU address when a GEM BO is assigned a GPU address and the kernel
> +PPGTT is named per-process it is actually per context. In legacy
> +(non-vm_bind) mode, when user space submits a batchbuffer, the kernel walks
> +the list of GEM buffer objects used by the batchbuffer and guarantees that
> +not only is the memory of each such GEM buffer object resident but it is
> +also present in the (PP)GTT. If the GEM buffer object is not yet placed in
> +the (PP)GTT, then it is given an address. Two consequences of this are: the
> +kernel needs to edit the batchbuffer submitted to write the correct value
> +of the GPU address when a GEM BO is assigned a GPU address and the kernel
>  might evict a different GEM BO from the (PP)GTT to make address room
>  for another GEM BO. Consequently, the ioctls submitting a batchbuffer
>  for execution also include a list of all locations within buffers that
> @@ -407,6 +411,15 @@ objects, which has the goal to make space in gpu virtual address spaces.
>  .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
>     :internal:
>  
> +VM_BIND mode
> +------------
> +
> +.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
> +   :doc: VM_BIND/UNBIND ioctls
> +
> +.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
> +   :internal:
> +
>  Batchbuffer Parsing
>  -------------------
>  
> @@ -419,11 +432,38 @@ Batchbuffer Parsing
>  User Batchbuffer Execution
>  --------------------------
>  
> +Client state
> +~~~~~~~~~~~~
> +
>  .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_context_types.h
>  
> +User command execution
> +~~~~~~~~~~~~~~~~~~~~~~
> +
>  .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>     :doc: User command execution
>  
> +User command execution in vm_bind mode
> +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> +
> +.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
> +   :doc: User command execution in vm_bind mode
> +
> +Common execbuff utilities
> +~~~~~~~~~~~~~~~~~~~~~~~~~
> +
> +.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_execbuffer_common.h
> +   :internal:
> +
> +.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_execbuffer_common.c
> +   :internal:
> +
> +Execbuf3 ioctl path
> +~~~~~~~~~~~~~~~~~~~
> +
> +.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
> +   :internal:
> +
>  Scheduling
>  ----------
>  .. kernel-doc:: drivers/gpu/drm/i915/i915_scheduler_types.h
> -- 
> 2.21.0.rc0.32.g243a4c7e27

  reply	other threads:[~2023-02-02 16:39 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-18  7:15 [Intel-gfx] [PATCH v10 00/23] drm/i915/vm_bind: Add VM_BIND functionality Niranjana Vishwanathapura
2023-01-18  7:15 ` [Intel-gfx] [PATCH v10 01/23] drm/i915/vm_bind: Expose vm lookup function Niranjana Vishwanathapura
2023-01-18  7:15 ` [Intel-gfx] [PATCH v10 02/23] drm/i915/vm_bind: Add __i915_sw_fence_await_reservation() Niranjana Vishwanathapura
2023-02-01 17:14   ` Andi Shyti
2023-01-18  7:15 ` [Intel-gfx] [PATCH v10 03/23] drm/i915/vm_bind: Expose i915_gem_object_max_page_size() Niranjana Vishwanathapura
2023-02-01 17:23   ` Andi Shyti
2023-01-18  7:15 ` [Intel-gfx] [PATCH v10 04/23] drm/i915/vm_bind: Support partially mapped vma resource Niranjana Vishwanathapura
2023-02-01 17:25   ` Andi Shyti
2023-01-18  7:15 ` [Intel-gfx] [PATCH v10 05/23] drm/i915/vm_bind: Add support to create persistent vma Niranjana Vishwanathapura
2023-01-18  7:15 ` [Intel-gfx] [PATCH v10 06/23] drm/i915/vm_bind: Implement bind and unbind of object Niranjana Vishwanathapura
2023-01-18  7:15 ` [Intel-gfx] [PATCH v10 07/23] drm/i915/vm_bind: Support for VM private BOs Niranjana Vishwanathapura
2023-01-18  7:15 ` [Intel-gfx] [PATCH v10 08/23] drm/i915/vm_bind: Add support to handle object evictions Niranjana Vishwanathapura
2023-01-18  7:15 ` [Intel-gfx] [PATCH v10 09/23] drm/i915/vm_bind: Support persistent vma activeness tracking Niranjana Vishwanathapura
2023-01-18  7:15 ` [Intel-gfx] [PATCH v10 10/23] drm/i915/vm_bind: Add out fence support Niranjana Vishwanathapura
2023-01-18  7:15 ` [Intel-gfx] [PATCH v10 11/23] drm/i915/vm_bind: Abstract out common execbuf functions Niranjana Vishwanathapura
2023-01-18  7:15 ` [Intel-gfx] [PATCH v10 12/23] drm/i915/vm_bind: Use common execbuf functions in execbuf path Niranjana Vishwanathapura
2023-02-02 16:04   ` Andi Shyti
2023-01-18  7:15 ` [Intel-gfx] [PATCH v10 13/23] drm/i915/vm_bind: Implement I915_GEM_EXECBUFFER3 ioctl Niranjana Vishwanathapura
2023-01-18  7:16 ` [Intel-gfx] [PATCH v10 14/23] drm/i915/vm_bind: Update i915_vma_verify_bind_complete() Niranjana Vishwanathapura
2023-01-18  7:16 ` [Intel-gfx] [PATCH v10 15/23] drm/i915/vm_bind: Expose i915_request_await_bind() Niranjana Vishwanathapura
2023-01-18  7:16 ` [Intel-gfx] [PATCH v10 16/23] drm/i915/vm_bind: Handle persistent vmas in execbuf3 Niranjana Vishwanathapura
2023-01-18  7:16 ` [Intel-gfx] [PATCH v10 17/23] drm/i915/vm_bind: userptr dma-resv changes Niranjana Vishwanathapura
2023-01-18  7:16 ` [Intel-gfx] [PATCH v10 18/23] drm/i915/vm_bind: Limit vm_bind mode to non-recoverable contexts Niranjana Vishwanathapura
2023-02-02 16:11   ` Andi Shyti
2023-01-18  7:16 ` [Intel-gfx] [PATCH v10 19/23] drm/i915/vm_bind: Add uapi for user to enable vm_bind_mode Niranjana Vishwanathapura
2023-01-18  7:16 ` [Intel-gfx] [PATCH v10 20/23] drm/i915/vm_bind: Render VM_BIND documentation Niranjana Vishwanathapura
2023-02-02 16:38   ` Andi Shyti [this message]
2023-01-18  7:16 ` [Intel-gfx] [PATCH v10 21/23] drm/i915/vm_bind: Async vm_unbind support Niranjana Vishwanathapura
2023-01-18  7:16 ` [Intel-gfx] [PATCH v10 22/23] drm/i915/vm_bind: Properly build persistent map sg table Niranjana Vishwanathapura
2023-01-18 12:49   ` Matthew Auld
2023-02-02 16:51   ` Andi Shyti
2023-01-18  7:16 ` [Intel-gfx] [PATCH v10 23/23] drm/i915/vm_bind: Support capture of persistent mappings Niranjana Vishwanathapura
2023-01-18 12:45   ` Matthew Auld
2023-01-18 18:19     ` Niranjana Vishwanathapura
2023-01-18 12:46   ` kernel test robot
2023-01-18 20:27   ` kernel test robot
2023-02-02 17:03   ` Andi Shyti
2023-01-18  8:17 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/vm_bind: Add VM_BIND functionality (rev13) Patchwork
2023-01-18  8:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-01-19  8:03 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-02-02  1:54 ` [Intel-gfx] [PATCH v10 00/23] drm/i915/vm_bind: Add VM_BIND functionality Zanoni, Paulo R
2023-04-13 18:51 ` Niranjana Vishwanathapura

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