From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915: Avoid div-by-zero on gen2
Date: Mon, 22 Mar 2021 16:48:44 +0200 [thread overview]
Message-ID: <YFiuTGbrhSR+eKK/@intel.com> (raw)
In-Reply-To: <161634423285.31629.4117583325553566238@build.alporthouse.com>
On Sun, Mar 21, 2021 at 04:30:32PM +0000, Chris Wilson wrote:
> Quoting Chris Wilson (2021-03-21 16:28:07)
> > Quoting Ville Syrjala (2021-03-21 16:10:38)
> > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > > index ec28a6cde49b..0b2434e29d00 100644
> > > --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > > @@ -189,7 +189,7 @@ compute_partial_view(const struct drm_i915_gem_object *obj,
> > > struct i915_ggtt_view view;
> > >
> > > if (i915_gem_object_is_tiled(obj))
> > > - chunk = roundup(chunk, tile_row_pages(obj));
> > > + chunk = roundup(chunk, tile_row_pages(obj) ?: 1);
> >
> > I was thinking the answer would be to align to the next page, and hey
> > presto!
>
> Wait, the tile row cannot be a single page. Something else is zero that
> should not be.
How come? At least i915_tiling_ok() doesn't enforce any
bigger lower bound.
--
Ville Syrjälä
Intel
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next prev parent reply other threads:[~2021-03-22 14:48 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-21 16:10 [Intel-gfx] [PATCH] drm/i915: Avoid div-by-zero on gen2 Ville Syrjala
2021-03-21 16:28 ` Chris Wilson
2021-03-21 16:30 ` Chris Wilson
2021-03-21 16:32 ` Chris Wilson
2021-03-22 14:48 ` Ville Syrjälä [this message]
2021-03-23 11:18 ` Chris Wilson
2021-03-21 16:47 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2021-03-21 18:06 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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