From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Jani Nikula <jani.nikula@intel.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
manasi.d.navare@intel.com
Subject: Re: [Intel-gfx] [PATCH v3 05/13] drm/i915/dg2: add DG2+ TRANS_DDI_FUNC_CTL DP 2.0 128b/132b mode
Date: Fri, 17 Sep 2021 15:54:52 +0300 [thread overview]
Message-ID: <YUSQHIR1puK6OHHR@intel.com> (raw)
In-Reply-To: <260e4da302d47ae50122eb8d517be6ac3ccb15f2.1631191763.git.jani.nikula@intel.com>
On Thu, Sep 09, 2021 at 03:51:57PM +0300, Jani Nikula wrote:
> Unfortunately, the DP 2.0 128b/132b DDI mode selection in the register
> conflicts with FDI. Since we have to deal with both meanings in the same
> code, for different platforms, clarify the macro name so we don't
> forget.
>
> Bspec: 50493
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> 2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 23ef291f7b30..2361f48537b5 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -489,7 +489,7 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
> if (crtc_state->hdmi_high_tmds_clock_ratio)
> temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
> } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
> - temp |= TRANS_DDI_MODE_SELECT_FDI;
> + temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
> temp |= (crtc_state->fdi_lanes - 1) << 1;
> } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
> temp |= TRANS_DDI_MODE_SELECT_DP_MST;
> @@ -679,7 +679,7 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
> ret = false;
> break;
>
> - case TRANS_DDI_MODE_SELECT_FDI:
> + case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
> ret = type == DRM_MODE_CONNECTOR_VGA;
> break;
>
> @@ -3558,7 +3558,7 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
> pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
> pipe_config->lane_count = 4;
> break;
> - case TRANS_DDI_MODE_SELECT_FDI:
> + case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
> pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
> break;
> case TRANS_DDI_MODE_SELECT_DP_SST:
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c2853cc005ee..03a94389c514 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10202,7 +10202,7 @@ enum skl_power_gate {
> #define TRANS_DDI_MODE_SELECT_DVI (1 << 24)
> #define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24)
> #define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24)
> -#define TRANS_DDI_MODE_SELECT_FDI (4 << 24)
> +#define TRANS_DDI_MODE_SELECT_FDI_OR_128B132B (4 << 24)
> #define TRANS_DDI_BPC_MASK (7 << 20)
> #define TRANS_DDI_BPC_8 (0 << 20)
> #define TRANS_DDI_BPC_10 (1 << 20)
> --
> 2.30.2
--
Ville Syrjälä
Intel
next prev parent reply other threads:[~2021-09-17 12:55 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-09 12:51 [Intel-gfx] [PATCH v3 00/13] drm/i915/dp: dp 2.0 enabling prep work Jani Nikula
2021-09-09 12:51 ` [Intel-gfx] [PATCH v3 01/13] drm/dp: add DP 2.0 UHBR link rate and bw code conversions Jani Nikula
2021-09-17 12:40 ` Ville Syrjälä
2021-09-09 12:51 ` [Intel-gfx] [PATCH v3 02/13] drm/dp: use more of the extended receiver cap Jani Nikula
2021-09-09 16:18 ` Lyude Paul
2021-09-09 16:18 ` Lyude Paul
2021-09-09 12:51 ` [Intel-gfx] [PATCH v3 03/13] drm/dp: add LTTPR DP 2.0 DPCD addresses Jani Nikula
2021-09-21 22:58 ` Nathan Chancellor
2021-09-22 0:45 ` Stephen Rothwell
2021-09-22 11:10 ` Jani Nikula
2021-09-22 13:49 ` Alex Deucher
2021-09-22 17:32 ` [Intel-gfx] [PATCH] drm/amd/display: Only define DP 2.0 symbols if not already defined Harry Wentland
2021-09-09 12:51 ` [Intel-gfx] [PATCH v3 04/13] drm/dp: add helper for extracting adjust 128b/132b TX FFE preset Jani Nikula
2021-09-09 12:51 ` [Intel-gfx] [PATCH v3 05/13] drm/i915/dg2: add DG2+ TRANS_DDI_FUNC_CTL DP 2.0 128b/132b mode Jani Nikula
2021-09-17 12:54 ` Ville Syrjälä [this message]
2021-09-09 12:51 ` [Intel-gfx] [PATCH v3 06/13] drm/i915/dp: add helper for checking for UHBR link rate Jani Nikula
2021-09-17 12:41 ` Ville Syrjälä
2021-09-09 12:51 ` [Intel-gfx] [PATCH v3 07/13] drm/i915/dp: use 128b/132b TPS2 for UHBR+ link rates Jani Nikula
2021-09-09 12:52 ` [Intel-gfx] [PATCH v3 08/13] drm/i915/dp: select 128b/132b channel encoding for UHBR rates Jani Nikula
2021-09-09 12:52 ` [Intel-gfx] [PATCH v3 09/13] drm/i915/dg2: configure TRANS_DP2_CTL for DP 2.0 Jani Nikula
2021-09-09 12:52 ` [Intel-gfx] [PATCH v3 10/13] drm/i915/dp: add HAS_DP20 macro Jani Nikula
2021-09-17 12:42 ` Ville Syrjälä
2021-09-09 12:52 ` [Intel-gfx] [PATCH v3 11/13] drm/i915/dg2: use 128b/132b transcoder DDI mode Jani Nikula
2021-09-17 12:51 ` Ville Syrjälä
2021-09-09 12:52 ` [Intel-gfx] [PATCH v3 12/13] drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH, LOW} for 128b/132b Jani Nikula
2021-09-17 12:53 ` Ville Syrjälä
2021-09-21 8:44 ` Jani Nikula
2021-09-09 12:52 ` [Intel-gfx] [PATCH v3 13/13] drm/i915/dg2: update link training " Jani Nikula
2021-09-09 13:48 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp: dp 2.0 enabling prep work (rev3) Patchwork
2021-09-09 13:50 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-09-09 14:17 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-09 16:25 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-09-17 12:54 ` [Intel-gfx] [PATCH v3 00/13] drm/i915/dp: dp 2.0 enabling prep work Jani Nikula
2021-09-17 16:56 ` Maxime Ripard
2021-09-21 8:44 ` Jani Nikula
2021-09-22 12:54 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/dp: dp 2.0 enabling prep work (rev4) Patchwork
2021-09-22 18:24 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/dp: dp 2.0 enabling prep work (rev5) Patchwork
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