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From: Andi Shyti <andi@etezian.org>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: Andi Shyti <andi@etezian.org>,
	Intel GFX <intel-gfx@lists.freedesktop.org>,
	DRI Devel <dri-devel@lists.freedesktop.org>,
	Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>,
	Chris Wilson <chris@chris-wilson.co.uk>,
	Lucas De Marchi <lucas.demarchi@intel.com>,
	Andi Shyti <andi.shyti@intel.com>
Subject: Re: [Intel-gfx] [PATCH v3] drm/i915/gt: move remaining debugfs interfaces into gt
Date: Fri, 8 Oct 2021 22:46:25 +0200	[thread overview]
Message-ID: <YWCuIb1wZU6+e57D@jack.zhora.eu> (raw)
In-Reply-To: <YWB0+Bls9kvUUk9z@intel.com>

Hi Ville,

> > +	if (IS_CHERRYVIEW(i915)) {
> > +		seq_printf(m, "Master Interrupt Control:\t%08x\n",
> > +			   intel_uncore_read(uncore, GEN8_MASTER_IRQ));
> > +
> > +		for (i = 0; i < 4; i++) {
> > +			seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
> > +				   i, intel_uncore_read(uncore,
> > +							GEN8_GT_IMR(i)));
> > +			seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
> > +				   i, intel_uncore_read(uncore,
> > +							GEN8_GT_IIR(i)));
> > +			seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
> > +				   i, intel_uncore_read(uncore,
> > +							GEN8_GT_IER(i)));
> > +		}
> > +
> 
> Why does chv get its own block? Looks identical to the bdw block.

[...]

> > +	} else if (!HAS_PCH_SPLIT(i915)) {
> 
> HAS_PCH_SPLIT in gt code looks a bit out of place.
> 
> > +		seq_printf(m, "Interrupt enable:    %08x\n",
> > +			   intel_uncore_read(uncore, GEN2_IER));
> > +		seq_printf(m, "Interrupt identity:  %08x\n",
> > +			   intel_uncore_read(uncore, GEN2_IIR));
> > +		seq_printf(m, "Interrupt mask:      %08x\n",
> > +			   intel_uncore_read(uncore, GEN2_IMR));
> 
> Technically on gen2 these are 16 bits, on gen3+ 32 bits. I don't
> quite remember now what happens when you read them as 32bit on gen2.
> Might be the msbs just come out all zeroes.
> 
> > +	} else {
> > +		seq_printf(m, "Graphics Interrupt enable:		%08x\n",
> > +			   intel_uncore_read(uncore, GTIER));
> > +		seq_printf(m, "Graphics Interrupt identity:		%08x\n",
> > +			   intel_uncore_read(uncore, GTIIR));
> > +		seq_printf(m, "Graphics Interrupt mask:		%08x\n",
> > +			   intel_uncore_read(uncore, GTIMR));
> 
> Probably this should be before the previous block to keep things in
> order. Also missing GEN6_PM stuff for snb+, and the master interrupt
> stuff for ilk+.

[...]

thanks for your input. Actually I'm not even sure this part of
the patch is required anymore. It was originally a copy paste of
the parts of the 'i915_interrupt_info' functions in the
'i915_gem_interrupt' debugfs file.

This file was removed here by Chris:

	cf977e18610e6 ("drm/i915/gem: Spring clean debugfs")

I have reproposed it in this patch seeking for comments because I
wanted to understand after all this time it might be needed or
not. If not I was going to remove it in my last version.

I haven't received any comments and therefore I am going to
remove it in v4.

Thank you,
Andi

  reply	other threads:[~2021-10-08 20:46 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-08 11:27 [Intel-gfx] [PATCH v3] drm/i915/gt: move remaining debugfs interfaces into gt Andi Shyti
2021-10-08 16:24 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: move remaining debugfs interfaces into gt (rev10) Patchwork
2021-10-08 16:42 ` [Intel-gfx] [PATCH v3] drm/i915/gt: move remaining debugfs interfaces into gt Ville Syrjälä
2021-10-08 20:46   ` Andi Shyti [this message]
2021-10-08 16:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: move remaining debugfs interfaces into gt (rev10) Patchwork
2021-10-08 22:09 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2020-03-31 16:45 [Intel-gfx] [PATCH v3] drm/i915/gt: move remaining debugfs interfaces into gt Andi Shyti
2020-03-31 16:53 ` Chris Wilson
2020-03-31 17:13   ` Andi Shyti
2020-03-31 17:16     ` Chris Wilson

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