Re: [Intel-gfx] [PATCH v5 05/10] drm/i915/hdcp: Consolidate HDCP setup/state cache

[Rodrigo Vivi <rodrigo.vivi@intel.com>]

On Mon, Apr 11, 2022 at 08:47:34PM +0000, Sean Paul wrote:
> From: Sean Paul <seanpaul@chromium.org>
> 
> Stick all of the setup for HDCP into a dedicated function. No functional
> change, but this will facilitate moving HDCP logic into helpers.


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>



> 
> Acked-by: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Sean Paul <seanpaul@chromium.org>
> Link: https://patchwork.freedesktop.org/patch/msgid/20210913175747.47456-6-sean@poorly.run #v1
> Link: https://patchwork.freedesktop.org/patch/msgid/20210915203834.1439-6-sean@poorly.run #v2
> Link: https://patchwork.freedesktop.org/patch/msgid/20211001151145.55916-6-sean@poorly.run #v3
> Link: https://patchwork.freedesktop.org/patch/msgid/20211105030434.2828845-6-sean@poorly.run #v4
> 
> Changes in v2:
> -None
> Changes in v3:
> -None
> Changes in v4:
> -None
> Changes in v5:
> -None
> ---
>  drivers/gpu/drm/i915/display/intel_hdcp.c | 52 +++++++++++++++--------
>  1 file changed, 35 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index 861c550b5bd6..6bb5a3971ed9 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -2167,6 +2167,37 @@ static enum mei_fw_tc intel_get_mei_fw_tc(enum transcoder cpu_transcoder)
>  	}
>  }
>  
> +static int
> +_intel_hdcp_setup(struct intel_connector *connector,
> +		  const struct intel_crtc_state *pipe_config, u8 content_type)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> +	struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> +	struct intel_hdcp *hdcp = &connector->hdcp;
> +	int ret = 0;
> +
> +	if (!connector->encoder) {
> +		drm_err(&dev_priv->drm, "[%s:%d] encoder is not initialized\n",
> +			connector->base.name, connector->base.base.id);
> +		return -ENODEV;
> +	}
> +
> +	hdcp->content_type = content_type;
> +
> +	if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) {
> +		hdcp->cpu_transcoder = pipe_config->mst_master_transcoder;
> +		hdcp->stream_transcoder = pipe_config->cpu_transcoder;
> +	} else {
> +		hdcp->cpu_transcoder = pipe_config->cpu_transcoder;
> +		hdcp->stream_transcoder = INVALID_TRANSCODER;
> +	}
> +
> +	if (DISPLAY_VER(dev_priv) >= 12)
> +		dig_port->hdcp_port_data.fw_tc = intel_get_mei_fw_tc(hdcp->cpu_transcoder);
> +
> +	return ret;
> +}
> +
>  static int initialize_hdcp_port_data(struct intel_connector *connector,
>  				     struct intel_digital_port *dig_port,
>  				     const struct intel_hdcp_shim *shim)
> @@ -2306,28 +2337,14 @@ int intel_hdcp_enable(struct intel_connector *connector,
>  	if (!hdcp->shim)
>  		return -ENOENT;
>  
> -	if (!connector->encoder) {
> -		drm_err(&dev_priv->drm, "[%s:%d] encoder is not initialized\n",
> -			connector->base.name, connector->base.base.id);
> -		return -ENODEV;
> -	}
> -
>  	mutex_lock(&hdcp->mutex);
>  	mutex_lock(&dig_port->hdcp_mutex);
>  	drm_WARN_ON(&dev_priv->drm,
>  		    hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED);
> -	hdcp->content_type = content_type;
> -
> -	if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) {
> -		hdcp->cpu_transcoder = pipe_config->mst_master_transcoder;
> -		hdcp->stream_transcoder = pipe_config->cpu_transcoder;
> -	} else {
> -		hdcp->cpu_transcoder = pipe_config->cpu_transcoder;
> -		hdcp->stream_transcoder = INVALID_TRANSCODER;
> -	}
>  
> -	if (DISPLAY_VER(dev_priv) >= 12)
> -		dig_port->hdcp_port_data.fw_tc = intel_get_mei_fw_tc(hdcp->cpu_transcoder);
> +	ret = _intel_hdcp_setup(connector, pipe_config, content_type);
> +	if (ret)
> +		goto out;
>  
>  	/*
>  	 * Considering that HDCP2.2 is more secure than HDCP1.4, If the setup
> @@ -2355,6 +2372,7 @@ int intel_hdcp_enable(struct intel_connector *connector,
>  					true);
>  	}
>  
> +out:
>  	mutex_unlock(&dig_port->hdcp_mutex);
>  	mutex_unlock(&hdcp->mutex);
>  	return ret;
> -- 
> Sean Paul, Software Engineer, Google / Chromium OS
>