From: Ramalingam C <ramalingam.c@intel.com>
To: Matthew Auld <matthew.auld@intel.com>
Cc: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915/ttm: remove calc_ctrl_surf_instr_size
Date: Mon, 8 Aug 2022 06:06:39 +0530 [thread overview]
Message-ID: <YvBal+4hwFIdcIjJ@ramaling-i9x> (raw)
In-Reply-To: <20220805132240.442747-1-matthew.auld@intel.com>
On 2022-08-05 at 14:22:39 +0100, Matthew Auld wrote:
> We only ever need to emit one ccs block copy command.
Since max size we handle at a time is CHUNK_SZ, we will need only one
cmd.
Reviewed-by: Ramalingam C<ramalingam.c@intel.com>
>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_migrate.c | 35 +++----------------------
> 1 file changed, 3 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
> index 9a0814422ba4..1bbed7aa436a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_migrate.c
> +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
> @@ -511,44 +511,16 @@ static inline u32 *i915_flush_dw(u32 *cmd, u32 flags)
> return cmd;
> }
>
> -static u32 calc_ctrl_surf_instr_size(struct drm_i915_private *i915, int size)
> -{
> - u32 num_cmds, num_blks, total_size;
> -
> - if (!GET_CCS_BYTES(i915, size))
> - return 0;
> -
> - /*
> - * XY_CTRL_SURF_COPY_BLT transfers CCS in 256 byte
> - * blocks. one XY_CTRL_SURF_COPY_BLT command can
> - * transfer upto 1024 blocks.
> - */
> - num_blks = DIV_ROUND_UP(GET_CCS_BYTES(i915, size),
> - NUM_CCS_BYTES_PER_BLOCK);
> - num_cmds = DIV_ROUND_UP(num_blks, NUM_CCS_BLKS_PER_XFER);
> - total_size = XY_CTRL_SURF_INSTR_SIZE * num_cmds;
> -
> - /*
> - * Adding a flush before and after XY_CTRL_SURF_COPY_BLT
> - */
> - total_size += 2 * MI_FLUSH_DW_SIZE;
> -
> - return total_size;
> -}
> -
> static int emit_copy_ccs(struct i915_request *rq,
> u32 dst_offset, u8 dst_access,
> u32 src_offset, u8 src_access, int size)
> {
> struct drm_i915_private *i915 = rq->engine->i915;
> int mocs = rq->engine->gt->mocs.uc_index << 1;
> - u32 num_ccs_blks, ccs_ring_size;
> + u32 num_ccs_blks;
> u32 *cs;
>
> - ccs_ring_size = calc_ctrl_surf_instr_size(i915, size);
> - WARN_ON(!ccs_ring_size);
> -
> - cs = intel_ring_begin(rq, round_up(ccs_ring_size, 2));
> + cs = intel_ring_begin(rq, 12);
> if (IS_ERR(cs))
> return PTR_ERR(cs);
>
> @@ -583,8 +555,7 @@ static int emit_copy_ccs(struct i915_request *rq,
> FIELD_PREP(XY_CTRL_SURF_MOCS_MASK, mocs);
>
> cs = i915_flush_dw(cs, MI_FLUSH_DW_LLC | MI_FLUSH_DW_CCS);
> - if (ccs_ring_size & 1)
> - *cs++ = MI_NOOP;
> + *cs++ = MI_NOOP;
>
> intel_ring_advance(rq, cs);
>
> --
> 2.37.1
>
prev parent reply other threads:[~2022-08-08 0:36 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-05 13:22 [Intel-gfx] [PATCH 1/2] drm/i915/ttm: remove calc_ctrl_surf_instr_size Matthew Auld
2022-08-05 13:22 ` [Intel-gfx] [PATCH 2/2] drm/i915/ttm: fix CCS handling Matthew Auld
2022-08-08 0:58 ` Ramalingam C
2022-08-05 14:39 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/ttm: remove calc_ctrl_surf_instr_size Patchwork
2022-08-05 15:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-08-05 21:23 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-08-08 0:36 ` Ramalingam C [this message]
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