From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: "20220801151616.12644-1-shawn.c.lee@intel.com"
<20220801151616.12644-1-shawn.c.lee@intel.com>
Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH] drm/i915/display: clear plane color control register when turn plane off
Date: Wed, 31 Aug 2022 16:43:54 +0300 [thread overview]
Message-ID: <Yw9lmnNLHBFztbMv@intel.com> (raw)
In-Reply-To: <BYAPR11MB2710024A8ACCD5C8F92A3E90A3789@BYAPR11MB2710.namprd11.prod.outlook.com>
On Wed, Aug 31, 2022 at 01:27:24PM +0000, Lee, Shawn C wrote:
> On Wed, August 31, 2022 8:33 PM, Ville Syrjälä wrote:
> >On Mon, Aug 01, 2022 at 11:16:16PM +0800, Lee Shawn C wrote:
> >> Customer report abnormal display output while switch eDP off sometimes.
> >> In current display disable flow, plane will be off at first. Then turn
> >> eDP off and disable HW pipe line. We found the abnormal pixel comes
> >> after turn plane off. Clear plane color ctl register when driver
> >> disable plane can solve this symptom.
> >>
> >> Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com>
> >> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/display/skl_universal_plane.c | 3 +++
> >> 1 file changed, 3 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> >> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> >> index caa03324a733..90977cfb7ebb 100644
> >> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> >> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> >> @@ -620,6 +620,8 @@ skl_plane_disable_arm(struct intel_plane *plane,
> >>
> >> intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0);
> >> intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0);
> >> + if (DISPLAY_VER(dev_priv) >= 10)
> >> + intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), 0);
> >> }
> >>
> >> static void
> >> @@ -638,6 +640,7 @@ icl_plane_disable_arm(struct intel_plane *plane,
> >> intel_psr2_disable_plane_sel_fetch(plane, crtc_state);
> >> intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0);
> >> intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0);
> >> + intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), 0);
> >
> >This makes no sense. The register value shouldn't even get latched since you wrote the arming register (PLANE_SURF) before this one.
> >
> >What platform is the problematic machine?
> >
>
> ADL-P
PSR related?
Do you have commit 031a2fea0482 ("drm/i915/psr: Disable PSR before disable pipe")?
--
Ville Syrjälä
Intel
next prev parent reply other threads:[~2022-08-31 13:44 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-01 15:16 [Intel-gfx] [PATCH] drm/i915/display: clear plane color control register when turn plane off Lee Shawn C
2022-08-01 21:27 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for " Patchwork
2022-08-31 12:33 ` [Intel-gfx] [PATCH] " Ville Syrjälä
2022-08-31 13:27 ` Lee, Shawn C
2022-08-31 13:43 ` Ville Syrjälä [this message]
2022-11-02 18:28 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/display: clear plane color control register when turn plane off (rev2) Patchwork
2022-11-02 18:50 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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