From: Andi Shyti <andi.shyti@linux.intel.com>
To: Badal Nilawar <badal.nilawar@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 0/6] i915: CAGF and RC6 changes for MTL
Date: Mon, 12 Sep 2022 13:18:52 +0200 [thread overview]
Message-ID: <Yx8VnClBmyDHCd3C@alfio.lan> (raw)
In-Reply-To: <20220909025646.3397620-1-badal.nilawar@intel.com>
Hi Badal,
you haven't Cc'ed anyone here... Please do CC the people
interested in the patches and dri-devel mailing list.
If you don't mind, could you please resend the series either as a
V2, if you are going to change something, or as a RESEND, if you
will not change anything?
Thanks,
Andi
On Fri, Sep 09, 2022 at 08:26:40AM +0530, Badal Nilawar wrote:
> This series includes the code changes to get CAGF, RC State and
> C6 Residency of MTL. The series depends on:
>
> https://patchwork.freedesktop.org/series/107908/
>
> We have included 3 patches from from the above series as part of this
> series in order for this series to compile. These are the first 3 patches
> authored by Matt Roper. Please do not review these first 3 patches. Only
> patch 4 and 6 needs review.
>
> v2: Included "Use GEN12 RPSTAT register" patch
>
> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
>
> Badal Nilawar (2):
> drm/i915/mtl: Modify CAGF functions for MTL
> drm/i915/mtl: Add C6 residency support for MTL SAMedia
>
> Don Hiatt (1):
> drm/i915: Use GEN12 RPSTAT register
>
> Matt Roper (3):
> drm/i915: Prepare more multi-GT initialization
> drm/i915: Rename and expose common GT early init routine
> drm/i915/xelpmp: Expose media as another GT
>
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_gt.c | 70 +++++++++++++++----
> drivers/gpu/drm/i915/gt/intel_gt.h | 2 +-
> drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 58 ++++++++++++++-
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 31 ++++++++
> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 9 ++-
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +
> drivers/gpu/drm/i915/gt/intel_rc6.c | 5 +-
> drivers/gpu/drm/i915/gt/intel_rps.c | 22 +++++-
> drivers/gpu/drm/i915/gt/intel_rps.h | 1 +
> drivers/gpu/drm/i915/gt/intel_sa_media.c | 39 +++++++++++
> drivers/gpu/drm/i915/gt/intel_sa_media.h | 15 ++++
> drivers/gpu/drm/i915/gt/selftest_rc6.c | 9 ++-
> drivers/gpu/drm/i915/i915_drv.h | 2 +
> drivers/gpu/drm/i915/i915_pci.c | 15 ++++
> drivers/gpu/drm/i915/i915_pmu.c | 11 ++-
> drivers/gpu/drm/i915/intel_device_info.h | 19 +++++
> drivers/gpu/drm/i915/intel_uncore.c | 16 ++++-
> drivers/gpu/drm/i915/intel_uncore.h | 20 +++++-
> .../gpu/drm/i915/selftests/mock_gem_device.c | 1 +
> 21 files changed, 325 insertions(+), 26 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.c
> create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.h
>
> --
> 2.25.1
next prev parent reply other threads:[~2022-09-12 11:19 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-09 2:56 [Intel-gfx] [PATCH 0/6] i915: CAGF and RC6 changes for MTL Badal Nilawar
2022-09-09 2:56 ` [Intel-gfx] [PATCH 1/6] drm/i915: Prepare more multi-GT initialization Badal Nilawar
2022-09-09 2:56 ` [Intel-gfx] [PATCH 2/6] drm/i915: Rename and expose common GT early init routine Badal Nilawar
2022-09-09 2:56 ` [Intel-gfx] [PATCH 3/6] drm/i915/xelpmp: Expose media as another GT Badal Nilawar
2022-09-09 2:56 ` [Intel-gfx] [PATCH 4/6] drm/i915: Use GEN12 RPSTAT register Badal Nilawar
2022-09-10 1:49 ` Dixit, Ashutosh
2022-09-12 11:29 ` Nilawar, Badal
2022-09-13 0:09 ` Dixit, Ashutosh
2022-09-13 7:47 ` Tvrtko Ursulin
2022-09-14 9:56 ` Nilawar, Badal
2022-09-14 16:11 ` Dixit, Ashutosh
2022-09-15 7:33 ` Tvrtko Ursulin
2022-09-09 2:56 ` [Intel-gfx] [PATCH 5/6] drm/i915/mtl: Modify CAGF functions for MTL Badal Nilawar
2022-09-09 2:56 ` [Intel-gfx] [PATCH 6/6] drm/i915/mtl: Add C6 residency support for MTL SAMedia Badal Nilawar
2022-09-10 3:38 ` Dixit, Ashutosh
2022-09-09 3:19 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: CAGF and RC6 changes for MTL (rev3) Patchwork
2022-09-09 3:19 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-09-09 3:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-09-09 8:23 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-09-12 11:18 ` Andi Shyti [this message]
2022-09-12 12:07 ` [Intel-gfx] [PATCH 0/6] i915: CAGF and RC6 changes for MTL Jani Nikula
2022-09-12 12:12 ` Nilawar, Badal
2022-09-12 17:16 ` Andi Shyti
2022-09-12 17:09 ` Andi Shyti
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=Yx8VnClBmyDHCd3C@alfio.lan \
--to=andi.shyti@linux.intel.com \
--cc=badal.nilawar@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox