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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Jani Nikula <jani.nikula@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 3/4] drm/i915: Pimp DPLL ref/unref debugs
Date: Thu, 22 Sep 2022 18:42:41 +0300	[thread overview]
Message-ID: <YyyCca+HGirPDS5o@intel.com> (raw)
In-Reply-To: <87mtar62py.fsf@intel.com>

On Thu, Sep 22, 2022 at 02:57:45PM +0300, Jani Nikula wrote:
> On Thu, 22 Sep 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > We currently have a debug message in intel_reference_shared_dpll()
> > but no counterpart in intel_unreference_shared_dpll(). Add one.
> >
> > Switch to the [CRTC:...] notation for the pipe name while at it.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 11 ++++++++---
> >  1 file changed, 8 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index e5fb66a5dd02..c21818cb6fe2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -384,20 +384,25 @@ intel_reference_shared_dpll(struct intel_atomic_state *state,
> >  	if (shared_dpll[id].pipe_mask == 0)
> >  		shared_dpll[id].hw_state = *pll_state;
> >  
> > -	drm_dbg(&i915->drm, "using %s for pipe %c\n", pll->info->name,
> > -		pipe_name(crtc->pipe));
> > -
> >  	shared_dpll[id].pipe_mask |= BIT(crtc->pipe);
> > +
> > +	drm_dbg(&i915->drm, "[CRTC:%d:%s] reserving %s\n",
> > +		crtc->base.base.id, crtc->base.name, pll->info->name);
> 
> 
> drm_dbg_kms while at it?

I shall blame this on tab completion stopping mid-sentence.

> 
> >  }
> >  
> >  static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
> >  					  const struct intel_crtc *crtc,
> >  					  const struct intel_shared_dpll *pll)
> >  {
> > +	struct drm_i915_private *i915 = to_i915(state->base.dev);
> >  	struct intel_shared_dpll_state *shared_dpll;
> >  
> >  	shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
> > +
> >  	shared_dpll[pll->info->id].pipe_mask &= ~BIT(crtc->pipe);
> > +
> > +	drm_dbg(&i915->drm, "[CRTC:%d:%s] releasing %s\n",
> > +		crtc->base.base.id, crtc->base.name, pll->info->name);
> >  }
> >  
> >  static void intel_put_dpll(struct intel_atomic_state *state,
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center

-- 
Ville Syrjälä
Intel

  reply	other threads:[~2022-09-22 15:43 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-21 21:15 [Intel-gfx] [PATCH 0/4] drm/i915: Fix TC port PLLs after readout Ville Syrjala
2022-09-21 21:15 ` [Intel-gfx] [PATCH 1/4] drm/i915: Force DPLL calculation for TC ports " Ville Syrjala
2022-09-22 11:56   ` Jani Nikula
2022-09-22 15:40     ` Ville Syrjälä
2022-09-22 19:12   ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2022-09-26 17:00     ` Jani Nikula
2022-09-21 21:15 ` [Intel-gfx] [PATCH 2/4] drm/i915: Don't bail early from intel_dp_initial_fastset_check() Ville Syrjala
2022-09-22 19:13   ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2022-09-21 21:15 ` [Intel-gfx] [PATCH 3/4] drm/i915: Pimp DPLL ref/unref debugs Ville Syrjala
2022-09-22 11:57   ` Jani Nikula
2022-09-22 15:42     ` Ville Syrjälä [this message]
2022-09-22 19:13   ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2022-09-21 21:15 ` [Intel-gfx] [PATCH 4/4] drm/i915: WARN if PLL ref/unref got messed up Ville Syrjala
2022-09-21 21:46 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Fix TC port PLLs after readout Patchwork
2022-09-21 22:10 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-09-22  0:45 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-09-22 23:05 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Fix TC port PLLs after readout (rev4) Patchwork
2022-09-22 23:24 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-09-23  6:09 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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