Intel-GFX Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v3 2/2] drm/i915/slpc: Update the frequency debugfs
Date: Thu, 6 Oct 2022 17:24:34 -0400	[thread overview]
Message-ID: <Yz9Hkhw7GO2ATCcQ@intel.com> (raw)
In-Reply-To: <20221005155943.34747-3-vinay.belgaumkar@intel.com>

On Wed, Oct 05, 2022 at 08:59:43AM -0700, Vinay Belgaumkar wrote:
> Read the values stored in the SLPC structures. Remove the
> fields that are no longer valid (like RPS interrupts) as
> well.
> 
> v2: Move all functionality changes to this patch (Jani)
> v3: Fix compile warning and if condition (Jani)
> 
> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_rps.c | 46 ++++++++++++++++++++++++++++-
>  1 file changed, 45 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> index 737db780db00..fc23c562d9b2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -2219,7 +2219,7 @@ u32 intel_rps_get_rpn_frequency(struct intel_rps *rps)
>  		return intel_gpu_freq(rps, rps->min_freq);
>  }
>  
> -void gen6_rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p)
> +static void rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p)
>  {
>  	struct intel_gt *gt = rps_to_gt(rps);
>  	struct drm_i915_private *i915 = gt->i915;
> @@ -2382,6 +2382,50 @@ void gen6_rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p)
>  		   intel_gpu_freq(rps, rps->efficient_freq));
>  }
>  
> +static void slpc_frequency_dump(struct intel_rps *rps, struct drm_printer *p)
> +{
> +	struct intel_gt *gt = rps_to_gt(rps);
> +	struct intel_uncore *uncore = gt->uncore;
> +	struct intel_rps_freq_caps caps;
> +	u32 pm_mask;
> +
> +	gen6_rps_get_freq_caps(rps, &caps);
> +	pm_mask = intel_uncore_read(uncore, GEN6_PMINTRMSK);
> +
> +	drm_printf(p, "PM MASK=0x%08x\n", pm_mask);
> +	drm_printf(p, "pm_intrmsk_mbz: 0x%08x\n",
> +		   rps->pm_intrmsk_mbz);
> +	drm_printf(p, "RPSTAT1: 0x%08x\n", intel_uncore_read(uncore, GEN6_RPSTAT1));
> +	drm_printf(p, "RPNSWREQ: %dMHz\n", intel_rps_get_requested_frequency(rps));
> +	drm_printf(p, "Lowest (RPN) frequency: %dMHz\n",
> +		   intel_gpu_freq(rps, caps.min_freq));
> +	drm_printf(p, "Nominal (RP1) frequency: %dMHz\n",
> +		   intel_gpu_freq(rps, caps.rp1_freq));
> +	drm_printf(p, "Max non-overclocked (RP0) frequency: %dMHz\n",
> +		   intel_gpu_freq(rps, caps.rp0_freq));
> +	drm_printf(p, "Current freq: %d MHz\n",
> +		   intel_rps_get_requested_frequency(rps));
> +	drm_printf(p, "Actual freq: %d MHz\n",
> +		   intel_rps_read_actual_frequency(rps));
> +	drm_printf(p, "Min freq: %d MHz\n",
> +		   intel_rps_get_min_frequency(rps));
> +	drm_printf(p, "Boost freq: %d MHz\n",
> +		   intel_rps_get_boost_frequency(rps));
> +	drm_printf(p, "Max freq: %d MHz\n",
> +		   intel_rps_get_max_frequency(rps));
> +	drm_printf(p,
> +		   "efficient (RPe) frequency: %d MHz\n",
> +		   intel_gpu_freq(rps, caps.rp1_freq));

Well, my feelings with these are:

1. We have these already in sysfs and we don't need to duplicated here.
But we have this already duplicated for years

2. We should probably simply remove this file when using SLPC and force
folks to look to the sysfs files?

3. Maybe we should take the simple lazy approach to just fix the values
that are wrong?

But well, we might end up bikeshedding this for years... At least the
new version for SLPC is clean, so I won't block.


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
(but I will hold the merge until tomorrow to see if anyone disagrees)


> +}
> +
> +void gen6_rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p)
> +{
> +	if (rps_uses_slpc(rps))
> +		return slpc_frequency_dump(rps, p);
> +	else
> +		return rps_frequency_dump(rps, p);
> +}
> +
>  static int set_max_freq(struct intel_rps *rps, u32 val)
>  {
>  	struct drm_i915_private *i915 = rps_to_i915(rps);
> -- 
> 2.35.1
> 

  reply	other threads:[~2022-10-06 21:24 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-05 15:59 [Intel-gfx] [PATCH v3 0/2] drm/i915/slpc: Update frequency debugfs for SLPC Vinay Belgaumkar
2022-10-05 15:59 ` [Intel-gfx] [PATCH v3 1/2] drm/i915: Add a wrapper for frequency debugfs Vinay Belgaumkar
2022-10-05 17:34   ` Jani Nikula
2022-10-05 17:35     ` Jani Nikula
2022-10-05 15:59 ` [Intel-gfx] [PATCH v3 2/2] drm/i915/slpc: Update the " Vinay Belgaumkar
2022-10-06 21:24   ` Rodrigo Vivi [this message]
2022-10-10 17:08     ` Rodrigo Vivi
2022-10-05 18:04 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/slpc: Update frequency debugfs for SLPC (rev4) Patchwork
2022-10-05 18:26 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-10-06  9:25 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=Yz9Hkhw7GO2ATCcQ@intel.com \
    --to=rodrigo.vivi@intel.com \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=vinay.belgaumkar@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox