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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Imre Deak <imre.deak@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 3/3] drm/i915: Fix idle pattern enabling
Date: Wed, 8 Mar 2023 23:28:07 +0200	[thread overview]
Message-ID: <ZAj8FHyaMWi+EGyY@intel.com> (raw)
In-Reply-To: <ZADzDhPBjkhNsT7+@ideak-desk.fi.intel.com>

On Thu, Mar 02, 2023 at 09:03:42PM +0200, Imre Deak wrote:
> On Tue, Feb 14, 2023 at 03:43:48PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Currently we are always switching to the idle pattern after the
> > link training, but we don't always wait for the minimum number
> > of idle patterns sent. That doesn't look to be what Bspec
> > asks of us.
> > 
> > According to bspec what we should do is switch to idle pattern
> > and wait for it only in DP1.4 MST cases. In all other cases we
> > should apparently do neither.
> > 
> > What confuses matters further is that the port sync SST sequence
> > asks us to "stay in idle pattern". But if we never switched to it
> > how can we stay in it? This still needs further clarificaiton.
> 
> HSW seems to require it also for SST, but yes for all other platforms
> bspec only requires it for MST.

commit 3ab9c63705cb ("drm/i915: hsw: fix link training for eDP on
port-A") (written by you it seems :) says there was some problem on
HSW that needed it for DDI A SST as well. But it's not really obvious
why you skipped the IDLE_DONE thing there. Maybe just an optimization?

Anyways, that does suggest that perhaps the current code is more
correct than what I'm proposing here.

> The DP2.1 standard has some addition
> (3.5.1.2.6) referring to idle pattern to be sent after TPS even for SST.
> Not sure if this would be done automatically by HW w/o manually
> switching to it.

I did at some point spot some DP state machine status bits in some
debug register. If I get bored I might see if I can spot the idle
pattern transmission on those when we don't explicitly enable it.

-- 
Ville Syrjälä
Intel

  reply	other threads:[~2023-03-08 21:33 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-14 13:43 [Intel-gfx] [PATCH 1/3] drm/i915: Don't switch to TPS1 when disabling DP_TP_CTL Ville Syrjala
2023-02-14 13:43 ` [Intel-gfx] [PATCH 2/3] drm/i915: Don't send idle pattern after DP2.0 link training Ville Syrjala
2023-03-02 18:54   ` Imre Deak
2023-02-14 13:43 ` [Intel-gfx] [PATCH 3/3] drm/i915: Fix idle pattern enabling Ville Syrjala
2023-03-02 19:03   ` Imre Deak
2023-03-08 21:28     ` Ville Syrjälä [this message]
2023-03-08 22:19       ` Imre Deak
2023-03-08 22:25         ` Ville Syrjälä
2023-02-14 15:26 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915: Don't switch to TPS1 when disabling DP_TP_CTL Patchwork
2023-02-14 15:50 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-02-15  3:22 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-03-02 18:53 ` [Intel-gfx] [PATCH 1/3] " Imre Deak
2023-03-07 16:26 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2023-03-07 22:07 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [v2,1/3] drm/i915: Don't switch to TPS1 when disabling DP_TP_CTL (rev2) Patchwork

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