From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v11 05/11] drm/i915/dp: Rearrange check for illegal mode and comments in mode_valid
Date: Fri, 17 Mar 2023 02:28:30 +0200 [thread overview]
Message-ID: <ZBO0Lv15lO0qBx7y@intel.com> (raw)
In-Reply-To: <20230314110415.2882484-6-ankit.k.nautiyal@intel.com>
On Tue, Mar 14, 2023 at 04:34:09PM +0530, Ankit Nautiyal wrote:
> Check for MODE_H_ILLEGAL before calculating max rates, lanes etc.
> Move comments about compressed bpp U6.4 format closer to where it is used.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index b49d113357e4..dcb3c2519041 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1098,6 +1098,9 @@ intel_dp_mode_valid(struct drm_connector *_connector,
> if (target_clock > max_dotclk)
> return MODE_CLOCK_HIGH;
>
> + if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
> + return MODE_H_ILLEGAL;
> +
> max_link_clock = intel_dp_max_link_rate(intel_dp);
> max_lanes = intel_dp_max_lane_count(intel_dp);
>
> @@ -1105,13 +1108,6 @@ intel_dp_mode_valid(struct drm_connector *_connector,
> mode_rate = intel_dp_link_required(target_clock,
> intel_dp_mode_min_output_bpp(connector, mode));
>
> - if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
> - return MODE_H_ILLEGAL;
> -
> - /*
> - * Output bpp is stored in 6.4 format so right shift by 4 to get the
> - * integer value since we support only integer values of bpp.
> - */
> if (HAS_DSC(dev_priv) &&
> drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
> /*
> @@ -1120,6 +1116,10 @@ intel_dp_mode_valid(struct drm_connector *_connector,
> */
> int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
>
> + /*
> + * Output bpp is stored in 6.4 format so right shift by 4 to get the
> + * integer value since we support only integer values of bpp.
> + */
> if (intel_dp_is_edp(intel_dp)) {
> dsc_max_output_bpp =
> drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
> --
> 2.25.1
--
Ville Syrjälä
Intel
next prev parent reply other threads:[~2023-03-17 0:28 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-14 11:04 [Intel-gfx] [PATCH v11 00/11] Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes Ankit Nautiyal
2023-03-14 11:04 ` [Intel-gfx] [PATCH v11 01/11] drm/i915/display: Add new member to configure PCON color conversion Ankit Nautiyal
2023-03-17 0:24 ` Ville Syrjälä
2023-03-17 10:07 ` Nautiyal, Ankit K
2023-03-17 11:39 ` Ville Syrjälä
2023-03-14 11:04 ` [Intel-gfx] [PATCH v11 02/11] drm/i915/display: Add new member in intel_dp to store ycbcr420 passthrough cap Ankit Nautiyal
2023-03-14 11:04 ` [Intel-gfx] [PATCH v11 03/11] drm/i915/dp: Replace intel_dp.dfp members with the new crtc_state sink_format Ankit Nautiyal
2023-03-16 23:46 ` Ville Syrjälä
2023-03-17 10:48 ` Nautiyal, Ankit K
2023-03-14 11:04 ` [Intel-gfx] [PATCH v11 04/11] drm/i915/display: Use sink_format instead of ycbcr420_output flag Ankit Nautiyal
2023-03-17 0:25 ` Ville Syrjälä
2023-03-17 11:10 ` Nautiyal, Ankit K
2023-03-14 11:04 ` [Intel-gfx] [PATCH v11 05/11] drm/i915/dp: Rearrange check for illegal mode and comments in mode_valid Ankit Nautiyal
2023-03-17 0:28 ` Ville Syrjälä [this message]
2023-03-14 11:04 ` [Intel-gfx] [PATCH v11 06/11] drm/i915/dp: Consider output_format while computing dsc bpp for mode_valid Ankit Nautiyal
2023-03-17 1:00 ` Ville Syrjälä
2023-03-20 3:36 ` Nautiyal, Ankit K
2023-03-20 8:26 ` Ville Syrjälä
2023-03-14 11:04 ` [Intel-gfx] [PATCH v11 07/11] drm/i915/display: Add helper function to check if sink_format is 420 Ankit Nautiyal
2023-03-14 11:04 ` [Intel-gfx] [PATCH v11 08/11] drm/i915/dp: Avoid DSC with output_format YCBCR420 Ankit Nautiyal
2023-03-14 17:33 ` Manasi Navare
2023-03-16 11:20 ` Nautiyal, Ankit K
2023-03-14 11:04 ` [Intel-gfx] [PATCH v11 09/11] drm/i915/dp: Handle BPP where HDMI2.1 DFP doesn't support DSC Ankit Nautiyal
2023-03-14 11:04 ` [Intel-gfx] [PATCH v11 10/11] drm/i915/dp: Fix FRL BW check for HDMI2.1 DFP Ankit Nautiyal
2023-03-14 11:04 ` [Intel-gfx] [PATCH v11 11/11] drm/i915/dp: Add a wrapper to check frl/tmds downstream constraints Ankit Nautiyal
2023-03-14 15:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes (rev12) Patchwork
2023-03-15 19:31 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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