From: "Lisovskiy, Stanislav" <stanislav.lisovskiy@intel.com>
To: Vinod Govindapillai <vinod.govindapillai@intel.com>
Cc: intel-gfx@lists.freedesktop.org, ville.syrjala@intel.com
Subject: Re: [Intel-gfx] [PATCH v1 2/2] drm/i915/reg: use the correct register to access SAGV block time
Date: Wed, 22 Mar 2023 10:26:39 +0200 [thread overview]
Message-ID: <ZBq7v3iSuHy91H3+@intel.com> (raw)
In-Reply-To: <20230322010138.663264-3-vinod.govindapillai@intel.com>
On Wed, Mar 22, 2023 at 03:01:38AM +0200, Vinod Govindapillai wrote:
> Wrong register address is used to read the SAG block time. Fix
> the register address according to the bspec.
>
> Bspec: 64608
>
> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ae8ba090c0f4..b2ed3c0fee4c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7716,7 +7716,7 @@ enum skl_power_gate {
> #define MTL_LATENCY_LEVEL_EVEN_MASK REG_GENMASK(12, 0)
> #define MTL_LATENCY_LEVEL_ODD_MASK REG_GENMASK(28, 16)
>
> -#define MTL_LATENCY_SAGV _MMIO(0x4578b)
> +#define MTL_LATENCY_SAGV _MMIO(0x4578c)
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> #define MTL_LATENCY_QCLK_SAGV REG_GENMASK(12, 0)
>
> #define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700)
> --
> 2.34.1
>
next prev parent reply other threads:[~2023-03-22 8:26 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-22 1:01 [Intel-gfx] [PATCH v1 0/2] Correction to QGV related register addresses Vinod Govindapillai
2023-03-22 1:01 ` [Intel-gfx] [PATCH v1 1/2] drm/i915/reg: fix QGV points register access offsets Vinod Govindapillai
2023-03-22 8:25 ` Lisovskiy, Stanislav
2023-03-22 1:01 ` [Intel-gfx] [PATCH v1 2/2] drm/i915/reg: use the correct register to access SAGV block time Vinod Govindapillai
2023-03-22 8:26 ` Lisovskiy, Stanislav [this message]
2023-03-22 14:03 ` Ville Syrjälä
2023-03-22 5:46 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Correction to QGV related register addresses Patchwork
2023-03-22 5:46 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-03-22 5:46 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2023-03-22 5:59 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-03-22 9:47 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=ZBq7v3iSuHy91H3+@intel.com \
--to=stanislav.lisovskiy@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=ville.syrjala@intel.com \
--cc=vinod.govindapillai@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox