From: Andi Shyti <andi.shyti@linux.intel.com>
To: fei.yang@intel.com
Cc: Matt Roper <matthew.d.roper@intel.com>,
intel-gfx@lists.freedesktop.org,
Lucas De Marchi <lucas.demarchi@intel.com>,
Madhumitha Tolakanahalli Pradeep
<madhumitha.tolakanahalli.pradeep@intel.com>,
dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 2/8] drm/i915/mtl: Define MOCS and PAT tables for MTL
Date: Wed, 19 Apr 2023 13:01:42 +0200 [thread overview]
Message-ID: <ZD/KFgdE4mtvKCPJ@ashyti-mobl2.lan> (raw)
In-Reply-To: <20230417062503.1884465-3-fei.yang@intel.com>
Hi Fei,
On Sun, Apr 16, 2023 at 11:24:57PM -0700, fei.yang@intel.com wrote:
> From: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com>
>
> On MTL, GT can no longer allocate on LLC - only the CPU can.
> This, along with addition of support for L4 cache calls a
> MOCS/PAT table update.
> Alos the PAT index registers are multicasted for primary GT,
/Alos/Also/
[...]
> +static void xelpmp_setup_private_ppat(struct intel_uncore *uncore)
> +{
> + intel_uncore_write(uncore, XELPMP_PAT_INDEX(0), MTL_PPAT_L4_0_WB);
> + intel_uncore_write(uncore, XELPMP_PAT_INDEX(1), MTL_PPAT_L4_1_WT);
> + intel_uncore_write(uncore, XELPMP_PAT_INDEX(2), MTL_PPAT_L4_3_UC);
> + intel_uncore_write(uncore, XELPMP_PAT_INDEX(3),
> + MTL_PPAT_L4_0_WB | MTL_2_COH_1W);
> + intel_uncore_write(uncore, XELPMP_PAT_INDEX(4),
> + MTL_PPAT_L4_0_WB | MTL_3_COH_2W);
nit: I think it's more readable if we either keep everything in
one line or we break the line for everyone. Even if we break the
80 characters rule.
[...]
> @@ -603,16 +639,22 @@ void setup_private_pat(struct intel_gt *gt)
>
> GEM_BUG_ON(GRAPHICS_VER(i915) < 8);
>
> - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
> - xehp_setup_private_ppat(gt);
> - else if (GRAPHICS_VER(i915) >= 12)
> - tgl_setup_private_ppat(uncore);
> - else if (GRAPHICS_VER(i915) >= 11)
> - icl_setup_private_ppat(uncore);
> - else if (IS_CHERRYVIEW(i915) || IS_GEN9_LP(i915))
> - chv_setup_private_ppat(uncore);
> - else
> - bdw_setup_private_ppat(uncore);
> + if (gt->type == GT_MEDIA) {
> + xelpmp_setup_private_ppat(gt->uncore);
nit: if you add a return here you save the else.
> + } else {
> + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
> + xelpg_setup_private_ppat(gt);
> + else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
> + xehp_setup_private_ppat(gt);
> + else if (GRAPHICS_VER(i915) >= 12)
> + tgl_setup_private_ppat(uncore);
> + else if (GRAPHICS_VER(i915) >= 11)
> + icl_setup_private_ppat(uncore);
> + else if (IS_CHERRYVIEW(i915) || IS_GEN9_LP(i915))
> + chv_setup_private_ppat(uncore);
> + else
> + bdw_setup_private_ppat(uncore);
> + }
[...]
> -static u32 global_mocs_offset(void)
> +static u32 global_mocs_offset(struct intel_gt *gt)
> {
> - return i915_mmio_reg_offset(GEN12_GLOBAL_MOCS(0));
> + return i915_mmio_reg_offset(GEN12_GLOBAL_MOCS(0)) + gt->uncore->gsi_offset;
There is one open question here coming from one of previous
Matt's reviews. Would it make sense to have this in a different
patch?
Andi
next prev parent reply other threads:[~2023-04-19 11:01 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-17 6:24 [Intel-gfx] [PATCH 0/8] drm/i915/mtl: Define MOCS and PAT tables for MTL fei.yang
2023-04-17 6:24 ` [Intel-gfx] [PATCH 1/8] drm/i915/mtl: Set has_llc=0 fei.yang
2023-04-19 10:59 ` Andi Shyti
2023-04-19 12:50 ` Andrzej Hajda
2023-04-19 14:10 ` Das, Nirmoy
2023-04-17 6:24 ` [Intel-gfx] [PATCH 2/8] drm/i915/mtl: Define MOCS and PAT tables for MTL fei.yang
2023-04-19 11:01 ` Andi Shyti [this message]
2023-04-19 16:00 ` Yang, Fei
2023-04-19 13:59 ` Andrzej Hajda
2023-04-19 16:03 ` Yang, Fei
2023-04-19 14:36 ` Das, Nirmoy
2023-04-19 16:05 ` Yang, Fei
2023-04-17 6:24 ` [Intel-gfx] [PATCH 3/8] drm/i915/mtl: Add PTE encode function fei.yang
2023-04-19 11:02 ` Andi Shyti
2023-04-19 12:51 ` Andrzej Hajda
2023-04-19 15:11 ` Das, Nirmoy
2023-04-17 6:24 ` [Intel-gfx] [PATCH 4/8] drm/i915/mtl: workaround coherency issue for Media fei.yang
2023-04-19 10:59 ` Andi Shyti
2023-04-19 12:38 ` Andi Shyti
2023-04-19 15:14 ` Das, Nirmoy
2023-04-19 15:40 ` Andrzej Hajda
2023-04-19 16:37 ` Yang, Fei
2023-04-19 18:49 ` Yang, Fei
2023-04-17 6:25 ` [Intel-gfx] [PATCH 5/8] drm/i915/mtl: end support for set caching ioctl fei.yang
2023-04-19 11:08 ` Andi Shyti
2023-04-19 13:05 ` Andrzej Hajda
2023-04-19 16:56 ` Yang, Fei
2023-04-17 6:25 ` [Intel-gfx] [PATCH 6/8] drm/i915: preparation for using PAT index fei.yang
2023-04-19 11:17 ` Andi Shyti
2023-04-17 6:25 ` [Intel-gfx] [PATCH 7/8] drm/i915: use pat_index instead of cache_level fei.yang
2023-04-19 12:16 ` Andi Shyti
2023-04-17 6:25 ` [Intel-gfx] [PATCH 8/8] drm/i915: Allow user to set cache at BO creation fei.yang
2023-04-19 12:23 ` Andi Shyti
2023-04-17 6:32 ` [Intel-gfx] [PATCH 0/8] drm/i915/mtl: Define MOCS and PAT tables for MTL Timo Aaltonen
2023-04-17 6:43 ` Yang, Fei
2023-04-24 20:00 ` Jordan Justen
2023-04-17 11:59 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/mtl: Define MOCS and PAT tables for MTL (rev5) Patchwork
2023-04-17 11:59 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-04-17 12:15 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2023-04-19 18:09 [Intel-gfx] [PATCH 0/8] drm/i915/mtl: Define MOCS and PAT tables for MTL fei.yang
2023-04-19 18:09 ` [Intel-gfx] [PATCH 2/8] " fei.yang
2023-04-19 21:12 [Intel-gfx] [PATCH 0/8] " fei.yang
2023-04-19 21:12 ` [Intel-gfx] [PATCH 2/8] " fei.yang
2023-04-19 21:48 ` Andi Shyti
2023-04-19 23:00 ` Yang, Fei
2023-04-19 21:59 ` Andi Shyti
2023-04-19 23:00 [Intel-gfx] [PATCH 0/8] " fei.yang
2023-04-19 23:00 ` [Intel-gfx] [PATCH 2/8] " fei.yang
2023-04-20 20:29 ` Matt Roper
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