Re: [Intel-gfx] [PATCH v3 02/12] drm/i915: Make the CRTC state consistent during sanitize-disabling

[Imre Deak <imre.deak@intel.com>]

On Tue, May 09, 2023 at 05:45:31PM +0300, Ville Syrjälä wrote:
> On Fri, May 05, 2023 at 11:46:04PM +0300, Imre Deak wrote:
> > Make sure that the CRTC state is reset correctly, as expected after
> > disabling the CRTC.
> > 
> > In particular this change will:
> > - Zero all the CSC blob pointers after intel_crtc_free_hw_state()
> >   has freed them.
> > - Zero the shared DPLL and port PLL pointers and clear the
> >   corresponding CRTC reference flag in the PLL state.
> > - Reset all the transcoder and pipe fields.
> > 
> > v2:
> > - Reset fully the CRTC state. (Ville)
> > - Clear pipe active flags in the DPLL state.
> > 
> > v3:
> > - Clear only the CRTC reference flag and add a helper for this.
> >   (Ville)
> > 
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 23 +++++++++++++------
> >  drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  3 +++
> >  .../drm/i915/display/intel_modeset_setup.c    | 13 ++++++-----
> >  3 files changed, 26 insertions(+), 13 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index ed372d227aa73..e436127bfe94e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -374,22 +374,31 @@ intel_reference_shared_dpll(struct intel_atomic_state *state,
> >  		    crtc->base.base.id, crtc->base.name, pll->info->name);
> >  }
> 
> Can you do the same for the reference counterpart for symmetry?

Yes, makes sense.

> I'd also split this refactoring from the functional stuff.

Ok. Patch 12 v3 also has an issue I noticed/commented on only after
sending it, if there's no other feedback on that one, I'll resend the
patchset with the above two also updated.

> With that
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> > +void
> > +intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
> > +				   const struct intel_shared_dpll *pll,
> > +				   struct intel_shared_dpll_state *shared_dpll_state)
> > +{
> > +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > +
> > +	drm_WARN_ON(&i915->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) == 0);
> > +
> > +	shared_dpll_state->pipe_mask &= ~BIT(crtc->pipe);
> > +
> > +	drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] releasing %s\n",
> > +		    crtc->base.base.id, crtc->base.name, pll->info->name);
> > +}
> > +
> >  static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
> >  					  const struct intel_crtc *crtc,
> >  					  const struct intel_shared_dpll *pll)
> >  {
> > -	struct drm_i915_private *i915 = to_i915(state->base.dev);
> >  	struct intel_shared_dpll_state *shared_dpll;
> >  	const enum intel_dpll_id id = pll->info->id;
> >  
> >  	shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
> >  
> > -	drm_WARN_ON(&i915->drm, (shared_dpll[id].pipe_mask & BIT(crtc->pipe)) == 0);
> > -
> > -	shared_dpll[id].pipe_mask &= ~BIT(crtc->pipe);
> > -
> > -	drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] releasing %s\n",
> > -		    crtc->base.base.id, crtc->base.name, pll->info->name);
> > +	intel_unreference_shared_dpll_crtc(crtc, pll, &shared_dpll[id]);
> >  }
> >  
> >  static void intel_put_dpll(struct intel_atomic_state *state,
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > index 3854f1b4299ac..ba62eb5d7c517 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > @@ -341,6 +341,9 @@ int intel_reserve_shared_dplls(struct intel_atomic_state *state,
> >  			       struct intel_encoder *encoder);
> >  void intel_release_shared_dplls(struct intel_atomic_state *state,
> >  				struct intel_crtc *crtc);
> > +void intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
> > +					const struct intel_shared_dpll *pll,
> > +					struct intel_shared_dpll_state *shared_dpll_state);
> >  void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
> >  			      enum icl_port_dpll_id port_dpll_id);
> >  void intel_update_active_dpll(struct intel_atomic_state *state,
> > diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > index eefa4018dc0c2..6e55806bbe066 100644
> > --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > @@ -88,13 +88,14 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
> >  	crtc->active = false;
> >  	crtc->base.enabled = false;
> >  
> > -	drm_WARN_ON(&i915->drm,
> > -		    drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0);
> > -	crtc_state->uapi.active = false;
> > -	crtc_state->uapi.connector_mask = 0;
> > -	crtc_state->uapi.encoder_mask = 0;
> > +	if (crtc_state->shared_dpll)
> > +		intel_unreference_shared_dpll_crtc(crtc,
> > +						   crtc_state->shared_dpll,
> > +						   &crtc_state->shared_dpll->state);
> > +
> > +	__drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
> >  	intel_crtc_free_hw_state(crtc_state);
> > -	memset(&crtc_state->hw, 0, sizeof(crtc_state->hw));
> > +	intel_crtc_state_reset(crtc_state, crtc);
> >  
> >  	for_each_encoder_on_crtc(&i915->drm, &crtc->base, encoder)
> >  		encoder->base.crtc = NULL;
> > -- 
> > 2.37.2
> 
> -- 
> Ville Syrjälä
> Intel