Re: [Intel-gfx] [PATCH] drm/i915/gt: drop dependency on VLV_DISPLAY_BASE

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Thu, May 11, 2023 at 03:31:16PM +0300, Jani Nikula wrote:
> On Thu, 11 May 2023, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Thu, May 11, 2023 at 12:04:27PM +0300, Jani Nikula wrote:
> >> CHV_FUSE_GT (0x182168) is purely about GT fuses, therefore belongs in
> >> intel_gt_regs.h, is in the gcfgmmio unit, but is technically in the VLV
> >> display base area.
> >> 
> >> Use the 0x182168 MMIO address directly to drop dependency on
> >> VLV_DISPLAY_BASE and thus display/intel_display_reg_defs.h in
> >> intel_gt_regs.h.
> >> 
> >> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +--
> >>  1 file changed, 1 insertion(+), 2 deletions(-)
> >> 
> >> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> >> index b8a39c219b60..f38550dae6b8 100644
> >> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> >> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> >> @@ -7,7 +7,6 @@
> >>  #define __INTEL_GT_REGS__
> >>  
> >>  #include "i915_reg_defs.h"
> >> -#include "display/intel_display_reg_defs.h"	/* VLV_DISPLAY_BASE */
> >>  
> >>  /*
> >>   * The perf control registers are technically multicast registers, but the
> >> @@ -1469,7 +1468,7 @@
> >>  #define GEN12_RCU_MODE				_MMIO(0x14800)
> >>  #define   GEN12_RCU_MODE_CCS_ENABLE		REG_BIT(0)
> >>  
> >> -#define CHV_FUSE_GT				_MMIO(VLV_DISPLAY_BASE + 0x2168)
> >> +#define CHV_FUSE_GT				_MMIO(0x182168)
> >
> > Or mmaybe s/VLV_DISPLAY_BASE/VLV_GUNIT_BASE/ here? Although all the
> > other Gunit register defintions are still in i915_reg.h, and using
> > VLV_DISPLAY_BASE. Not sure what to do about all that...
> 
> Works for me, as long as I can drop the dependency on
> display/intel_display_reg_defs.h.
> 
> Just let me know.

I'd probably go with the VLV_GUNIT_BASE approach. We can think
about what to do with all the other Gunit registers later.

> 
> BR,
> Jani.
> 
> 
> >
> >>  #define   CHV_FGT_DISABLE_SS0			(1 << 10)
> >>  #define   CHV_FGT_DISABLE_SS1			(1 << 11)
> >>  #define   CHV_FGT_EU_DIS_SS0_R0_SHIFT		16
> >> -- 
> >> 2.39.2
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center

-- 
Ville Syrjälä
Intel