From: Andi Shyti <andi.shyti@linux.intel.com>
To: "Upadhyay, Tejas" <tejas.upadhyay@intel.com>
Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH V2] drm/i915/gt: Add workaround 14016712196
Date: Wed, 31 May 2023 12:33:59 +0200 [thread overview]
Message-ID: <ZHcil9Bb0vSpH6TK@ashyti-mobl2.lan> (raw)
In-Reply-To: <SJ1PR11MB6204E0F351F3BDA0727E71EA81489@SJ1PR11MB6204.namprd11.prod.outlook.com>
Hi Tejas,
> >
> > I'm wondering, though, if we can put both dummy pipe and real pipe in the
> > same command and advance the ring only once at the end... nevermind.
>
> As we have conditional ring increments, we cant decide ring size at start in ring begin for whole bunch at once. Though double checking.
yes, you add it conditionally. Check, e.g., the control:
if (!HAS_FLAT_CCS(rq->engine->i915))
count = 8 + 4;
else
count = 8;
In the second if block. You are basically doing the same thing.
But I'm not strong with this.
Andi
next prev parent reply other threads:[~2023-05-31 10:34 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-17 13:22 [Intel-gfx] [PATCH V2] drm/i915/gt: Add workaround 14016712196 Tejas Upadhyay
2023-05-17 17:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Add workaround 14016712196 (rev2) Patchwork
2023-05-18 6:54 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-05-30 21:05 ` [Intel-gfx] [PATCH V2] drm/i915/gt: Add workaround 14016712196 Andi Shyti
2023-05-31 10:14 ` Upadhyay, Tejas
2023-05-31 10:33 ` Andi Shyti [this message]
2023-05-31 11:52 ` Andrzej Hajda
2023-05-31 12:14 ` Andi Shyti
2023-05-31 12:48 ` Upadhyay, Tejas
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