Re: [Intel-gfx] [v7, 9/9] drm/i915/gt: Support aux invalidation on all engines

[Andi Shyti <andi.shyti@linux.intel.com>]

Hi Janusz,

> > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > index 3ded597f002a2..30fb4e0af6134 100644
> > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > @@ -165,9 +165,36 @@ static u32 preparser_disable(bool state)
> >  	return MI_ARB_CHECK | 1 << 8 | state;
> >  }
> >  
> > -u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv_reg)
> > +static i915_reg_t gen12_get_aux_inv_reg(struct intel_engine_cs *engine)
> >  {
> > -	u32 gsi_offset = gt->uncore->gsi_offset;
> > +	if (!HAS_AUX_CCS(engine->i915))
> > +		return INVALID_MMIO_REG;
> > +
> > +	switch (engine->id) {
> > +	case RCS0:
> > +		return GEN12_CCS_AUX_INV;
> > +	case BCS0:
> > +		return GEN12_BCS0_AUX_INV;
> > +	case VCS0:
> > +		return GEN12_VD0_AUX_INV;
> > +	case VCS2:
> > +		return GEN12_VD2_AUX_INV;
> > +	case VECS0:
> > +		return GEN12_VE0_AUX_INV;
> > +	case CCS0:
> > +		return GEN12_CCS0_AUX_INV;
> > +	default:
> > +		return INVALID_MMIO_REG;
> > +	}
> > +}
> > +
> > +u32 *gen12_emit_aux_table_inv(struct intel_engine_cs *engine, u32 *cs)
> > +{
> > +	i915_reg_t inv_reg = gen12_get_aux_inv_reg(engine);
> > +	u32 gsi_offset = engine->gt->uncore->gsi_offset;
> > +
> > +	if (i915_mmio_reg_valid(inv_reg))
> > +		return cs;
> 
> Is that correct?  Now the original body of gen12_emit_aux_table_inv() will be 
> executed only if either (!HAS_AUX_CCS(engine->i915) or the engine is not one 
> of (RCS0, BCS0, VCS0, VCS2 or CCS0), ...
> 
> >  
> >  	*cs++ = MI_LOAD_REGISTER_IMM(1) | MI_LRI_MMIO_REMAP_EN;
> >  	*cs++ = i915_mmio_reg_offset(inv_reg) + gsi_offset;
> > @@ -201,6 +228,11 @@ static u32 *intel_emit_pipe_control_cs(struct i915_request *rq, u32 bit_group_0,
> >  	return cs;
> >  }
> >  
> > +static bool gen12_engine_has_aux_inv(struct intel_engine_cs *engine)
> > +{
> > +	return i915_mmio_reg_valid(gen12_get_aux_inv_reg(engine));
> > +}
> > +
> >  static int mtl_dummy_pipe_control(struct i915_request *rq)
> >  {
> >  	/* Wa_14016712196 */
> > @@ -307,11 +339,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
> >  
> >  		cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);
> >  
> > -		if (!HAS_FLAT_CCS(rq->engine->i915)) {
> 
> ... while before it was executed only if (!HAS_FLAT_CCS(rq->engine->i915)), 
> which, according to commit description of PATCH 2/9, rather had the opposite 
> meaning.  Am I missing something?

flat_ccs and aux_ccs are not mutually exclusive, so far the can
both miss like in PVC. So that the !HAS_FLAT_CCS() is an
approximation and that's why we need a better evaluation.

Aux invalidation is needed only on platforms from TGL and beyond
excluding PVC. The above engines  are the only engines where AUX
invalidation happens, but there are no cases when we reach the
default condition, as the emit_flush_rcs is already called within
that set of engines. The default is there just for completeness.

Does this answer?

Thanks,
Andi