Re: [Intel-gfx] [PATCH 2/4] drm/i915/irq: add dg1_de_irq_postinstall()

[Rodrigo Vivi <rodrigo.vivi@intel.com>]

On Tue, Aug 08, 2023 at 06:53:29PM +0300, Jani Nikula wrote:
> Add a dedicated de postinstall function.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_display_irq.c    | 17 ++++++++++++++++-
>  .../gpu/drm/i915/display/intel_display_irq.h    |  2 +-
>  drivers/gpu/drm/i915/i915_irq.c                 | 11 +----------
>  3 files changed, 18 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index 168f6d4ce208..a706ba740dd6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -1666,7 +1666,7 @@ void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>  	}
>  }
>  
> -void mtp_irq_postinstall(struct drm_i915_private *i915)
> +static void mtp_irq_postinstall(struct drm_i915_private *i915)

should this be in a separated patch?

up to you,
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

>  {
>  	struct intel_uncore *uncore = &i915->uncore;
>  	u32 sde_mask = SDE_GMBUS_ICP | SDE_PICAINTERRUPT;
> @@ -1699,6 +1699,21 @@ void gen11_de_irq_postinstall(struct drm_i915_private *dev_priv)
>  			   GEN11_DISPLAY_IRQ_ENABLE);
>  }
>  
> +void dg1_de_irq_postinstall(struct drm_i915_private *i915)
> +{
> +	if (!HAS_DISPLAY(i915))
> +		return;
> +
> +	if (DISPLAY_VER(i915) >= 14)
> +		mtp_irq_postinstall(i915);
> +	else
> +		icp_irq_postinstall(i915);
> +
> +	gen8_de_irq_postinstall(i915);
> +	intel_uncore_write(&i915->uncore, GEN11_DISPLAY_INT_CTL,
> +			   GEN11_DISPLAY_IRQ_ENABLE);
> +}
> +
>  void intel_display_irq_init(struct drm_i915_private *i915)
>  {
>  	i915->drm.vblank_disable_immediate = true;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
> index 8a2d069d3aac..ce190557826b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
> @@ -62,8 +62,8 @@ void ibx_irq_postinstall(struct drm_i915_private *i915);
>  void vlv_display_irq_postinstall(struct drm_i915_private *i915);
>  void icp_irq_postinstall(struct drm_i915_private *i915);
>  void gen8_de_irq_postinstall(struct drm_i915_private *i915);
> -void mtp_irq_postinstall(struct drm_i915_private *i915);
>  void gen11_de_irq_postinstall(struct drm_i915_private *i915);
> +void dg1_de_irq_postinstall(struct drm_i915_private *i915);
>  
>  u32 i915_pipestat_enable_mask(struct drm_i915_private *i915, enum pipe pipe);
>  void i915_enable_pipestat(struct drm_i915_private *i915, enum pipe pipe, u32 status_mask);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 1723c215dcf6..8c074643b6d1 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -869,16 +869,7 @@ static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
>  
>  	GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
>  
> -	if (HAS_DISPLAY(dev_priv)) {
> -		if (DISPLAY_VER(dev_priv) >= 14)
> -			mtp_irq_postinstall(dev_priv);
> -		else
> -			icp_irq_postinstall(dev_priv);
> -
> -		gen8_de_irq_postinstall(dev_priv);
> -		intel_uncore_write(&dev_priv->uncore, GEN11_DISPLAY_INT_CTL,
> -				   GEN11_DISPLAY_IRQ_ENABLE);
> -	}
> +	dg1_de_irq_postinstall(dev_priv);
>  
>  	dg1_master_intr_enable(intel_uncore_regs(uncore));
>  	intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
> -- 
> 2.39.2
>