Intel-GFX Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Manasi Navare <navaremanasi@chromium.org>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 1/6] drm/i915: Move psr unlock out from the pipe update critical section
Date: Tue, 29 Aug 2023 11:23:56 +0300	[thread overview]
Message-ID: <ZO2rHIflHTJ_KN_O@intel.com> (raw)
In-Reply-To: <CAE72mNkp72Od5DyOKM0Qw4ekMA4iXOc=2B9Pa8mJonZ0=F5_xg@mail.gmail.com>

On Mon, Aug 28, 2023 at 11:16:13AM -0700, Manasi Navare wrote:
> By doing psr_unlock after the vblank evade, are we ensuring that even
> when VRR params change during the pipe update, psr unlock will
> happen after the actual vblank  based on newly programmed VRR params?

The unlock will happen as soon as the new register values have been
written. The vblank will happen when it happens, could be asap or could
be much later.

I don't actually even know what this PSR lock is protecting, I suppose
it's trying to prevent muckery with the PSR hw state while the update
is being programmed. Shrug.

> 
> Manasi
> 
> On Sun, Aug 27, 2023 at 10:41 PM Ville Syrjala
> <ville.syrjala@linux.intel.com> wrote:
> >
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Do the PSR unlock after the vblank evade critcal section is
> > fully over, not before.
> >
> > Cc: Manasi Navare <navaremanasi@chromium.org>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_crtc.c | 9 +++++----
> >  1 file changed, 5 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> > index 182c6dd64f47..5caa928e5ce9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> > @@ -646,10 +646,8 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
> >         ktime_t end_vbl_time = ktime_get();
> >         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >
> > -       intel_psr_unlock(new_crtc_state);
> > -
> >         if (new_crtc_state->do_async_flip)
> > -               return;
> > +               goto out;
> >
> >         trace_intel_pipe_update_end(crtc, end_vbl_count, scanline_end);
> >
> > @@ -709,7 +707,7 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
> >         local_irq_enable();
> >
> >         if (intel_vgpu_active(dev_priv))
> > -               return;
> > +               goto out;
> >
> >         if (crtc->debug.start_vbl_count &&
> >             crtc->debug.start_vbl_count != end_vbl_count) {
> > @@ -724,4 +722,7 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
> >         }
> >
> >         dbg_vblank_evade(crtc, end_vbl_time);
> > +
> > +out:
> > +       intel_psr_unlock(new_crtc_state);
> >  }
> > --
> > 2.41.0
> >

-- 
Ville Syrjälä
Intel

  reply	other threads:[~2023-08-29  8:24 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-28  5:41 [Intel-gfx] [PATCH 0/6] drm/i915: VRR and M/N stuff Ville Syrjala
2023-08-28  5:41 ` [Intel-gfx] [PATCH 1/6] drm/i915: Move psr unlock out from the pipe update critical section Ville Syrjala
2023-08-28 18:16   ` Manasi Navare
2023-08-29  8:23     ` Ville Syrjälä [this message]
2023-08-28  5:41 ` [Intel-gfx] [PATCH 2/6] drm/i915: Change intel_pipe_update_{start, end}() calling convention Ville Syrjala
2023-08-28 18:30   ` Manasi Navare
2023-08-29  8:27     ` Ville Syrjälä
2023-08-28  5:41 ` [Intel-gfx] [PATCH 3/6] drm/i915: Extract intel_crtc_vblank_evade_scanlines() Ville Syrjala
2023-08-28 18:31   ` Manasi Navare
2023-08-28  5:41 ` [Intel-gfx] [PATCH 4/6] drm/i915: Enable VRR later during fastsets Ville Syrjala
2023-08-28 18:47   ` Manasi Navare
2023-08-29  8:26     ` Ville Syrjälä
2023-08-29 14:58       ` Manasi Navare
2023-08-30  5:12         ` Ville Syrjälä
2023-09-11 18:21   ` Golani, Mitulkumar Ajitkumar
2023-08-28  5:41 ` [Intel-gfx] [PATCH 5/6] drm/i915: Adjust seamless_m_n flag behaviour Ville Syrjala
2023-08-28 16:58   ` Golani, Mitulkumar Ajitkumar
2023-08-29  8:20     ` Ville Syrjälä
2023-08-29 13:48       ` Golani, Mitulkumar Ajitkumar
2023-08-30  5:16         ` Ville Syrjälä
2023-08-30  6:51           ` Golani, Mitulkumar Ajitkumar
2023-08-30  6:58             ` Ville Syrjälä
2023-08-30  7:32               ` Golani, Mitulkumar Ajitkumar
2023-08-28  5:41 ` [Intel-gfx] [PATCH 6/6] drm/i915: Optimize out redundant M/N updates Ville Syrjala
2023-08-28  6:11 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: VRR and M/N stuff Patchwork
2023-08-28  6:29 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-08-28  8:03 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=ZO2rHIflHTJ_KN_O@intel.com \
    --to=ville.syrjala@linux.intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=navaremanasi@chromium.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox