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From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Mika Kahola <mika.kahola@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v3] drm/i915/display: Reset message bus after each read/write operation
Date: Mon, 16 Oct 2023 14:10:58 -0400	[thread overview]
Message-ID: <ZS18stantS5d8c+7@intel.com> (raw)
In-Reply-To: <20231016125544.719963-1-mika.kahola@intel.com>

On Mon, Oct 16, 2023 at 03:55:44PM +0300, Mika Kahola wrote:
> Every know and then we receive the following error when running
> for example IGT test kms_flip.
> 
> [drm] *ERROR* PHY G Read 0d80 failed after 3 retries.
> [drm] *ERROR* PHY G Write 0d81 failed after 3 retries.
> 
> Since the error is sporadic in nature, the patch proposes
> to reset the message bus after every successful or unsuccessful
> read or write operation.
> 
> v2: Add FIXME's to indicate the experimental nature of
>     this workaround (Rodrigo)
> v3: Dropping the additional delay as moving reset to *_read_once()
>     and *_write_once() functions seem unnecessary delay
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 6e6a1818071e..9e24f820d4cf 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -206,6 +206,13 @@ static int __intel_cx0_read_once(struct drm_i915_private *i915, enum port port,
>  
>  	intel_clear_response_ready_flag(i915, port, lane);
>  
> +	/*
> +	 * FIXME: Workaround to let HW to settle
> +	 * down and let the message bus to end up
> +	 * in a known state
> +	 */
> +	intel_cx0_bus_reset(i915, port, lane);
> +
>  	return REG_FIELD_GET(XELPDP_PORT_P2M_DATA_MASK, val);
>  }
>  
> @@ -285,6 +292,13 @@ static int __intel_cx0_write_once(struct drm_i915_private *i915, enum port port,
>  
>  	intel_clear_response_ready_flag(i915, port, lane);
>  
> +	/*
> +	 * FIXME: Workaround to let HW to settle
> +	 * down and let the message bus to end up
> +	 * in a known state
> +	 */
> +	intel_cx0_bus_reset(i915, port, lane);
> +
>  	return 0;
>  }
>  
> -- 
> 2.34.1
> 

  reply	other threads:[~2023-10-16 18:11 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-16 12:55 [Intel-gfx] [PATCH v3] drm/i915/display: Reset message bus after each read/write operation Mika Kahola
2023-10-16 18:10 ` Rodrigo Vivi [this message]
2023-10-17  2:28 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display: Reset message bus after each read/write operation (rev4) Patchwork
2023-10-17  6:53   ` Kahola, Mika
2023-10-17 13:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-10-17 16:15 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-10-18 21:20 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Reset message bus after each read/write operation (rev5) Patchwork
2023-10-19  0:08 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-10-19 11:38 ` Patchwork
2023-10-19 12:06 ` Patchwork
2023-10-19 12:51 ` Patchwork
2023-10-25  5:29 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork

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