Intel-GFX Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Jani Nikula <jani.nikula@intel.com>
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Subject: Re: [PATCH v3 3/9] drm/i915/pps: only touch the vlv_ members on VLV/CHV
Date: Wed, 18 Sep 2024 22:13:35 +0300	[thread overview]
Message-ID: <ZusmX8cRJHIKRAx8@intel.com> (raw)
In-Reply-To: <158c7b30e56d22aa3f9c9e51e87b9d89687d74d5.1726681620.git.jani.nikula@intel.com>

On Wed, Sep 18, 2024 at 08:47:43PM +0300, Jani Nikula wrote:
> While the struct intel_pps vlv_pps_pipe and vlv_active_pipe members are
> only relevant for VLV/CHV, we still initialize them on all platforms and
> check them on BXT/GLK. Wrap all access inside VLV/CHV checks for
> consistency.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c  |  6 +++---
>  drivers/gpu/drm/i915/display/intel_pps.c | 11 ++++++-----
>  2 files changed, 9 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 9dd86523012f..9f908dbd45ea 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -6867,8 +6867,6 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
>  		return false;
>  
>  	intel_dp->reset_link_params = true;
> -	intel_dp->pps.vlv_pps_pipe = INVALID_PIPE;
> -	intel_dp->pps.vlv_active_pipe = INVALID_PIPE;
>  
>  	/* Preserve the current hw state. */
>  	intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
> @@ -6895,8 +6893,10 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
>  	intel_dp_set_default_sink_rates(intel_dp);
>  	intel_dp_set_default_max_sink_lane_count(intel_dp);
>  
> -	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> +	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> +		intel_dp->pps.vlv_pps_pipe = INVALID_PIPE;
>  		intel_dp->pps.vlv_active_pipe = vlv_active_pipe(intel_dp);
> +	}
>  
>  	intel_dp_aux_init(intel_dp);
>  	intel_connector->dp.dsc_decompression_aux = &intel_dp->aux;
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
> index 2d8d911988ab..649dc6ad2278 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> @@ -472,16 +472,17 @@ void intel_pps_reset_all(struct intel_display *display)
>  	for_each_intel_dp(display->drm, encoder) {
>  		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  
> -		drm_WARN_ON(display->drm,
> -			    intel_dp->pps.vlv_active_pipe != INVALID_PIPE);
> +		if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> +			drm_WARN_ON(display->drm,
> +				    intel_dp->pps.vlv_active_pipe != INVALID_PIPE);

Might make sense to just split this whole function
into vlv/chv vs. bxt/glk versions. It's called from
platform specific code only so each caller knows
which one it wants.

Series is
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

>  
>  		if (encoder->type != INTEL_OUTPUT_EDP)
>  			continue;
>  
> -		if (DISPLAY_VER(display) >= 9)
> -			intel_dp->pps.bxt_pps_reset = true;
> -		else
> +		if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  			intel_dp->pps.vlv_pps_pipe = INVALID_PIPE;
> +		else
> +			intel_dp->pps.bxt_pps_reset = true;
>  	}
>  }
>  
> -- 
> 2.39.2

-- 
Ville Syrjälä
Intel

  reply	other threads:[~2024-09-18 19:13 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-09-18 17:47 [PATCH v3 0/9] drm/i915/pps: hide VLV/CHV PPS pipe stuff inside intel_pps.c Jani Nikula
2024-09-18 17:47 ` [PATCH v3 1/9] drm/i915/pps: add vlv_ prefix to pps_pipe and active_pipe members Jani Nikula
2024-09-18 17:47 ` [PATCH v3 2/9] drm/i915/pps: add bxt_ prefix to pps_reset Jani Nikula
2024-09-18 17:47 ` [PATCH v3 3/9] drm/i915/pps: only touch the vlv_ members on VLV/CHV Jani Nikula
2024-09-18 19:13   ` Ville Syrjälä [this message]
2024-09-19  9:13     ` Jani Nikula
2024-09-18 17:47 ` [PATCH v3 4/9] drm/i915/pps: add vlv_pps_pipe_init() Jani Nikula
2024-09-18 17:47 ` [PATCH v3 5/9] drm/i915/pps: add vlv_pps_pipe_reset() Jani Nikula
2024-09-18 17:47 ` [PATCH v3 6/9] drm/i915/pps: add vlv_pps_port_disable() Jani Nikula
2024-09-18 17:47 ` [PATCH v3 7/9] drm/i915/pps: rename vlv_pps_init() to vlv_pps_port_enable_unlocked() Jani Nikula
2024-09-18 17:47 ` [PATCH v3 8/9] drm/i915/pps: add vlv_pps_backlight_initial_pipe() Jani Nikula
2024-09-18 17:47 ` [PATCH v3 9/9] drm/i915/pps: move vlv_active_pipe() to intel_pps.c Jani Nikula
2024-09-18 18:50 ` ✗ Fi.CI.SPARSE: warning for drm/i915/pps: hide VLV/CHV PPS pipe stuff inside intel_pps.c (rev3) Patchwork
2024-09-18 18:59 ` ✓ Fi.CI.BAT: success " Patchwork
2024-09-19  7:03 ` ✗ Fi.CI.IGT: failure " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=ZusmX8cRJHIKRAx8@intel.com \
    --to=ville.syrjala@linux.intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=intel-xe@lists.freedesktop.org \
    --cc=jani.nikula@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox