From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
Cc: intel-gfx@lists.freedesktop.org, matthew.d.roper@intel.com,
ville.syrjala@intel.com
Subject: Re: [PATCH] drm/i915/icl: Update csc and gamma enable checks
Date: Thu, 3 Oct 2024 14:10:31 +0300 [thread overview]
Message-ID: <Zv57pzLX4ltH4w00@intel.com> (raw)
In-Reply-To: <20241003090341.3140997-1-sai.teja.pottumuttu@intel.com>
On Thu, Oct 03, 2024 at 02:33:41PM +0530, Sai Teja Pottumuttu wrote:
> With ICL, we have a way to check if gamma and csc are enabled on
> a pipe using bits in GAMMA_MODE and CSC_MODE. So, use them as well
> along with the existing BOTTOM_COLOR checks.
>
> BSpec: 7463, 7466
> Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 24 ++++++++++++++++++++--
> 1 file changed, 22 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 50f41aeb3c28..1bf36898dc7e 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1076,6 +1076,26 @@ static void skl_get_config(struct intel_crtc_state *crtc_state)
> crtc_state->csc_enable = true;
> }
>
> +static void icl_get_config(struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> + u32 bottom_color;
> +
> + crtc_state->gamma_mode = hsw_read_gamma_mode(crtc);
> + crtc_state->csc_mode = ilk_read_csc_mode(crtc);
> +
> + bottom_color = intel_de_read(i915, SKL_BOTTOM_COLOR(crtc->pipe));
> +
> + if ((bottom_color & SKL_BOTTOM_COLOR_GAMMA_ENABLE) ||
> + (crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE))
> + crtc_state->gamma_enable = true;
> +
> + if ((bottom_color & SKL_BOTTOM_COLOR_CSC_ENABLE) ||
> + (crtc_state->csc_mode & ICL_CSC_ENABLE))
> + crtc_state->csc_enable = true;
We don't use the old per-plane/bottom color way of enabling these.
So this is not right.
> +}
> +
> static void skl_color_commit_arm(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -3811,7 +3831,7 @@ static const struct intel_color_funcs tgl_color_funcs = {
> .read_luts = icl_read_luts,
> .lut_equal = icl_lut_equal,
> .read_csc = icl_read_csc,
> - .get_config = skl_get_config,
> + .get_config = icl_get_config,
> };
>
> static const struct intel_color_funcs icl_color_funcs = {
> @@ -3823,7 +3843,7 @@ static const struct intel_color_funcs icl_color_funcs = {
> .read_luts = icl_read_luts,
> .lut_equal = icl_lut_equal,
> .read_csc = icl_read_csc,
> - .get_config = skl_get_config,
> + .get_config = icl_get_config,
> };
>
> static const struct intel_color_funcs glk_color_funcs = {
> --
> 2.34.1
--
Ville Syrjälä
Intel
next prev parent reply other threads:[~2024-10-03 11:10 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-03 9:03 [PATCH] drm/i915/icl: Update csc and gamma enable checks Sai Teja Pottumuttu
2024-10-03 9:58 ` ✓ Fi.CI.BAT: success for " Patchwork
2024-10-03 10:46 ` [PATCH] " Jani Nikula
2024-10-03 11:10 ` Ville Syrjälä [this message]
2024-10-03 14:22 ` Matt Roper
2024-10-03 14:32 ` Ville Syrjälä
2024-10-03 14:58 ` Ville Syrjälä
2024-10-03 15:38 ` Pottumuttu, Sai Teja
2024-10-03 15:46 ` Ville Syrjälä
2024-10-03 15:56 ` Pottumuttu, Sai Teja
2024-10-03 16:02 ` Jani Nikula
2024-10-03 16:05 ` Matt Roper
2024-10-03 16:12 ` Ville Syrjälä
2024-10-03 16:20 ` Matt Roper
2024-10-03 16:43 ` Ville Syrjälä
2024-10-07 19:33 ` ✗ Fi.CI.IGT: failure for " Patchwork
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