Re: [RFC] Add AS_SDP to fastset

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Thu, Aug 08, 2024 at 03:18:49PM +0530, Mitul Golani wrote:
> Add full modeset being triggered during VRR enable/disable, specially
> when panel has Adaptive sync SDP suypport.
> 
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 2755ebbbb9d2..b41ea78d4c89 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5433,7 +5433,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  	PIPE_CONF_CHECK_INFOFRAME(hdmi);
>  	PIPE_CONF_CHECK_INFOFRAME(drm);
>  	PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
> -	PIPE_CONF_CHECK_DP_AS_SDP(as_sdp);
> +	if(!fastset)
> +		PIPE_CONF_CHECK_DP_AS_SDP(as_sdp);

What is needed is:
step 1: Fix vrr.vsync_{start,end} computation, and add them to
        the state checker + state dump. currently those depend on
	crtc_state->vrr.enable which is wrong
step 2: figure out what kind of sequencing requirements there
        for enabling/disabling the SDP vs. enabling/disabling 
	VRR, and then probably rewrite the hacky code that
	tries to updated infoframes during fastset to actually
	work properly

>  
>  	PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
>  	PIPE_CONF_CHECK_I(master_transcoder);
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel