From: "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>
To: Jani Nikula <jani.nikula@linux.intel.com>,
<dri-devel@lists.freedesktop.org>,
<intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH 1/2] drm/display/dp: Default 8 bpc support when DSC is supported
Date: Thu, 24 Aug 2023 17:11:56 +0530 [thread overview]
Message-ID: <a297d229-70b2-e29a-c65f-b68072e3fc89@intel.com> (raw)
In-Reply-To: <87lee04vuf.fsf@intel.com>
Thanks Jani for the corrections and suggestions.
I agree to them and will fix them in next version.
Now that I see the commit subject line also should have been "Assume 8
bpc support when DSC is supported", will change that too.
Regards,
Ankit
On 8/24/2023 3:15 PM, Jani Nikula wrote:
> On Thu, 24 Aug 2023, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
>> As per DP v1.4, a DP DSC Sink device shall support 8bpc in DPCD 6Ah.
>> Apparently some panels that do support DSC, are not setting the bit for
>> 8bpc.
>>
>> So always assume 8bpc support by DSC decoder, when DSC is claimed to be
>> supported.
>>
>> v2: Use helper to check dsc support. (Ankit)
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>> drivers/gpu/drm/display/drm_dp_helper.c | 9 +++++++--
>> 1 file changed, 7 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
>> index e6a78fd32380..309fc10cde78 100644
>> --- a/drivers/gpu/drm/display/drm_dp_helper.c
>> +++ b/drivers/gpu/drm/display/drm_dp_helper.c
>> @@ -2447,14 +2447,19 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
>> u8 dsc_bpc[3])
>> {
>> int num_bpc = 0;
>> +
>> + if(!drm_dp_sink_supports_dsc(dsc_dpcd))
> ^
>
> Missing space.
>
>> + return 0;
>> +
>> u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
> All declarations should be before code.
>
>>
>> if (color_depth & DP_DSC_12_BPC)
>> dsc_bpc[num_bpc++] = 12;
>> if (color_depth & DP_DSC_10_BPC)
>> dsc_bpc[num_bpc++] = 10;
>> - if (color_depth & DP_DSC_8_BPC)
>> - dsc_bpc[num_bpc++] = 8;
>> +
>> + /* A DP DSC Sink devices shall support 8 bpc. */
> Mixed singular and plural, a ... devices.
>
>> + dsc_bpc[num_bpc++] = 8;
>>
>> return num_bpc;
>> }
next prev parent reply other threads:[~2023-08-24 11:42 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-23 11:54 [Intel-gfx] [PATCH 0/2] eDP DSC fixes Ankit Nautiyal
2023-08-23 11:54 ` [Intel-gfx] [PATCH 1/2] drm/display/dp: Default 8 bpc support when DSC is supported Ankit Nautiyal
2023-08-23 16:26 ` kernel test robot
2023-08-24 3:47 ` Ankit Nautiyal
2023-08-24 9:45 ` Jani Nikula
2023-08-24 11:41 ` Nautiyal, Ankit K [this message]
2023-08-23 11:54 ` [Intel-gfx] [PATCH 2/2] drivers/drm/i915: Honor limits->max_bpp while computing DSC max input bpp Ankit Nautiyal
2023-08-24 9:29 ` Lisovskiy, Stanislav
2023-08-24 11:34 ` Nautiyal, Ankit K
2023-08-24 9:44 ` Jani Nikula
2023-08-24 11:37 ` Nautiyal, Ankit K
2023-08-23 13:02 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for eDP DSC fixes Patchwork
2023-08-23 13:02 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-08-23 13:20 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-08-24 4:31 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for eDP DSC fixes (rev2) Patchwork
2023-08-24 4:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-08-24 4:48 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-08-24 11:35 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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