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From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
To: Uma Shankar <uma.shankar@intel.com>, intel-gfx@lists.freedesktop.org
Cc: ville.syrjala@intel.com, maarten.lankhorst@intel.com
Subject: Re: [v9 1/2] drm/i915/icl: Define Plane Input CSC Coefficient Registers
Date: Fri, 2 Nov 2018 10:25:32 +0100	[thread overview]
Message-ID: <a6f38521-5db3-d3ea-3c55-15a1405aac97@linux.intel.com> (raw)
In-Reply-To: <1541099420-12419-2-git-send-email-uma.shankar@intel.com>

Op 01-11-18 om 20:10 schreef Uma Shankar:
> Defined the plane input csc coefficient registers and macros.
> 6 registers are used to program a total of 9 coefficients,
> added macros to define each of them for all the planes
> supporting the feature on pipes. On ICL, bottom 3 planes
> have this capability.
>
> v2: Segregated the register macro definition as separate patch
> as per Maarten's suggestion.
>
> v3: Removed a redundant 3rd Pipe register definition and
> simplified the equally spaced register definition by adding an
> offset as per Matt's comment.
>
> v4: No Change
>
> v5: Renamed the register Macro as per Matt's suggestion.
>
> v6: No Change
>
> v7: No Change
>
> v8: No Change
>
> v9: No Change
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
For both patches:
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
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  reply	other threads:[~2018-11-02  9:25 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-01 19:10 [v9 0/2] Enable Plane Input CSC for ICL Uma Shankar
2018-11-01 19:10 ` [v9 1/2] drm/i915/icl: Define Plane Input CSC Coefficient Registers Uma Shankar
2018-11-02  9:25   ` Maarten Lankhorst [this message]
2018-11-01 19:10 ` [v9 2/2] drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion Uma Shankar
2018-11-01 19:48 ` ✗ Fi.CI.CHECKPATCH: warning for Enable Plane Input CSC for ICL (rev8) Patchwork
2018-11-01 20:07 ` ✓ Fi.CI.BAT: success " Patchwork
2018-11-02  1:02 ` ✓ Fi.CI.IGT: " Patchwork

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