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From: "Hogander, Jouni" <jouni.hogander@intel.com>
To: "intel-xe@lists.freedesktop.org" <intel-xe@lists.freedesktop.org>,
	"Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"Deak, Imre" <imre.deak@intel.com>
Subject: Re: [PATCH 2/7] drm/i915/psr: Stop using intel_dsc_enabled_on_link to detect crtc DSC status
Date: Tue, 9 Jun 2026 13:30:59 +0000	[thread overview]
Message-ID: <a70165a374cc9f07f562d84b76e680134ea0a13b.camel@intel.com> (raw)
In-Reply-To: <52f74617-93ff-417c-a48d-4a2c58262e1f@intel.com>

On Tue, 2026-06-09 at 17:44 +0530, Nautiyal, Ankit K wrote:
> 
> On 6/8/2026 7:41 PM, Jouni Högander wrote:
> > Intel_dsc_enabled_on_link is not really about DSC being enabled on
> > crtc. It
> > is telling if FEC is enabled on link.
> 
> Hmm... This is a bit unclear to me.
> 
> As per commit 470b84af457e ("drm/i915/dp_mst: Recompute all MST link 
> CRTCs if DSC gets enabled on the link")
> 
> We wanted to do away with FEC tracking, and instead tracked DSC. FEC
> for 
> UHBR was not getting filled so it makes sense to track DSC (FEC being
> mandatory for DP DSC).
> 
>  From commit message for commit 470b84af457e
> 
> "...
> 
> Based on the above, to be able to determine the DSC state on both
> 
> non-UHBR and UHBR MST links, track the more generic DSC-enabled-on-
> link
> 
> state (instead of the FEC-enabled-on-link state) for each CRTC in
> 
> intel_link_bw_limits."
> 
> So to me it appears that we were actually concerned about DSC and not
> FEC and started using intel_dsc_enabled_on_link()
> 
> (later, fec_enable was unused and removed).
> 
> Perhaps I am missing some context?

It seems I made mistake in which patch I placed this change. I will fix
this in next version. I will propably move this part to next patch.

Anyways if you looks at what crtc_state-
>dsc.compression_enabled_on_link is about you find that it is really
about FEC being enabled on a link. If any single stream within link
needs FEC then FEC needs to be enabled on that link where the stream is
in.

DSC is a feature that needs FEC being enabled. This far mixing FEC and
DSC haven't caused any problems because DSC was the only feature which
needs FEC.

Now as Panel Replay comes into picture as a another feature which also
requires FEC being used we need to differentiate FEC and DSC. Patch 2
and 3 in this set are about this. Hopefully this helps.

BR,
Jouni Högander

> 
> > Instead of intel_dsc_enabled_on_link
> > check status directly from crtc->dsc.compression_enable.
> 
> I agree to this part though. We can separate it out in any case.
> 
> 
> Regards,
> 
> Ankit
> 
> > 
> > Also rename intel_dsc_enabled_on_link as intel_fec_enabled_on_link.
> > 
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> >   drivers/gpu/drm/i915/display/intel_psr.c  | 6 +++---
> >   drivers/gpu/drm/i915/display/intel_vdsc.c | 2 +-
> >   drivers/gpu/drm/i915/display/intel_vdsc.h | 2 +-
> >   3 files changed, 5 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index ad2f6c79f5808..f58200d38ac2c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -1740,7 +1740,7 @@ static bool
> > intel_sel_update_config_valid(struct intel_crtc_state *crtc_state,
> >   		if (!connector->dp.panel_replay_caps.su_support)
> >   			goto unsupported;
> >   
> > -		if (intel_dsc_enabled_on_link(crtc_state) &&
> > +		if (crtc_state->dsc.compression_enable &&
> >   		    connector->dp.panel_replay_caps.dsc_support !=
> >   		    INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE) {
> >   			drm_dbg_kms(display->drm,
> > @@ -1840,7 +1840,7 @@ static bool
> > _panel_replay_compute_config(struct intel_crtc_state *crtc_state,
> >   		return false;
> >   	}
> >   
> > -	if (intel_dsc_enabled_on_link(crtc_state) &&
> > +	if (crtc_state->dsc.compression_enable &&
> >   	    connector->dp.panel_replay_caps.dsc_support ==
> >   	    INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED) {
> >   		drm_dbg_kms(display->drm,
> > @@ -3235,7 +3235,7 @@ verify_panel_replay_dsc_state(const struct
> > intel_crtc_state *crtc_state)
> >   		return;
> >   
> >   	drm_WARN_ON(display->drm,
> > -		    intel_dsc_enabled_on_link(crtc_state) &&
> > +		    crtc_state->dsc.compression_enable &&
> >   		    crtc_state->panel_replay_dsc_support ==
> >   		    INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED);
> >   }
> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > index 8f06c3a4d56df..35c93fcbb6427 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > @@ -431,7 +431,7 @@ void intel_dsc_enable_on_crtc(struct
> > intel_crtc_state *crtc_state)
> >   	crtc_state->dsc.compression_enable = true;
> >   }
> >   
> > -bool intel_dsc_enabled_on_link(const struct intel_crtc_state
> > *crtc_state)
> > +bool intel_fec_enabled_on_link(const struct intel_crtc_state
> > *crtc_state)
> >   {
> >   	struct intel_display *display =
> > to_intel_display(crtc_state);
> >   
> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h
> > b/drivers/gpu/drm/i915/display/intel_vdsc.h
> > index 3372f8694054d..60d86399808c0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.h
> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
> > @@ -28,7 +28,7 @@ void intel_dsc_enable(const struct
> > intel_crtc_state *crtc_state);
> >   void intel_dsc_disable(const struct intel_crtc_state
> > *crtc_state);
> >   int intel_dsc_compute_params(struct intel_crtc_state
> > *pipe_config);
> >   void intel_dsc_enable_on_crtc(struct intel_crtc_state
> > *crtc_state);
> > -bool intel_dsc_enabled_on_link(const struct intel_crtc_state
> > *crtc_state);
> > +bool intel_fec_enabled_on_link(const struct intel_crtc_state
> > *crtc_state);
> >   void intel_dsc_get_config(struct intel_crtc_state *crtc_state);
> >   enum intel_display_power_domain
> >   intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder
> > cpu_transcoder);


  reply	other threads:[~2026-06-09 13:31 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-08 14:11 [PATCH 0/7] Enable FEC when using DP Panel Replay Jouni Högander
2026-06-08 14:11 ` [PATCH 1/7] drm/i915/psr: Check FEC support for " Jouni Högander
2026-06-09 11:29   ` Nautiyal, Ankit K
2026-06-08 14:11 ` [PATCH 2/7] drm/i915/psr: Stop using intel_dsc_enabled_on_link to detect crtc DSC status Jouni Högander
2026-06-09 12:14   ` Nautiyal, Ankit K
2026-06-09 13:30     ` Hogander, Jouni [this message]
2026-06-09 13:45   ` Imre Deak
2026-06-18  6:04     ` Hogander, Jouni
2026-06-08 14:11 ` [PATCH 3/7] drm/i915/display: Rename compression_enabled_on_link and link_dsc_pipes Jouni Högander
2026-06-08 14:11 ` [PATCH 4/7] drm/i915/psr: Split PSR compute config Jouni Högander
2026-06-08 14:11 ` [PATCH 5/7] drm/i915/psr: Move DP/eDP Panel Replay compute config to pre " Jouni Högander
2026-06-08 14:11 ` [PATCH 6/7] drm/i915/psr: Add PSR specific " Jouni Högander
2026-06-08 14:11 ` [PATCH 7/7] drm/i915/psr: Enable FEC if using DP Panel Replay Jouni Högander
2026-06-08 20:37 ` ✓ i915.CI.BAT: success for Enable FEC when " Patchwork
2026-06-09  1:44 ` ✗ i915.CI.Full: failure " Patchwork

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