From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2 6/7] drm/i915/execlists: Direct submission from irq handler
Date: Tue, 8 May 2018 12:53:30 +0100 [thread overview]
Message-ID: <a9966401-ecf3-4d1b-9e2f-7993cbc7e684@linux.intel.com> (raw)
In-Reply-To: <152577781760.24602.3562717670343027711@mail.alporthouse.com>
On 08/05/2018 12:10, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2018-05-08 11:54:27)
>>
>> On 07/05/2018 14:57, Chris Wilson wrote:
>>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>>> index f9bc3aaa90d0..775cf167d938 100644
>>> --- a/drivers/gpu/drm/i915/i915_irq.c
>>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>>> @@ -1465,19 +1465,18 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
>>> struct intel_engine_execlists * const execlists = &engine->execlists;
>>> bool tasklet = false;
>>>
>>> - if (iir & GT_CONTEXT_SWITCH_INTERRUPT) {
>>> - if (READ_ONCE(engine->execlists.active))
>>> - tasklet = !test_and_set_bit(ENGINE_IRQ_EXECLIST,
>>> - &engine->irq_posted);
>>> - }
>>> + if (iir & GT_CONTEXT_SWITCH_INTERRUPT && READ_ONCE(execlists->active))
>>> + tasklet = !test_and_set_bit(ENGINE_IRQ_EXECLIST,
>>> + &engine->irq_posted);
>>>
>>> if (iir & GT_RENDER_USER_INTERRUPT) {
>>> notify_ring(engine);
>>> - tasklet |= USES_GUC_SUBMISSION(engine->i915);
>>> + if (!test_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted))
>>> + tasklet = USES_GUC_SUBMISSION(engine->i915);
>>
>> I don't understand this change. In the GuC case IRQ_EXECLISTS is never
>> set so the conditional is pointeless. In execlist mode user interrupt
>> has nothing to do with scheduling the tasklet.
>
> Because notify_ring() may have just executed the tasklet and cleared the
> bit from irq_posted. I didn't want to then do a second dequeue.
But IRQ_EXECLISTS is never set in GuC mode. So set-if-clear in this case
is equivalent to unconditional-or.
If you want to clear the tasklet bool in execlist mode then this is
extremely non-obvious. More readable owuld be something like
if (iir & USER_IRQ)
tasklet = notify_ring(...) ? 0 : USES_GUC(...);
Where notify_ring would return true if it signalled anything.
We wouldn't know though if that means the tasklet actually ran. :(
Oh well.. put a comment please, because it really is non-obvious.
>>> static void gen8_gt_irq_ack(struct drm_i915_private *i915,
>>> diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c
>>> index 6bfe30af7826..7d4542b46f5e 100644
>>> --- a/drivers/gpu/drm/i915/intel_guc_submission.c
>>> +++ b/drivers/gpu/drm/i915/intel_guc_submission.c
>>> @@ -782,6 +782,8 @@ static void guc_submission_tasklet(unsigned long data)
>>> struct execlist_port *port = execlists->port;
>>> struct i915_request *rq;
>>>
>>> + clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
>>> +
>>
>> I don't understand this either - there is no changed code path which
>> sets this in GuC mode.
>
> The guc may takeover with the bit set. And since we aren't particularly
> careful with parking before takeover, it was prudent to always clear it
> here as a direct analogue to the execlists context switch handler.
Okay.
Regards,
Tvrtko
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next prev parent reply other threads:[~2018-05-08 11:53 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-07 13:57 [PATCH v2 1/7] drm/i915: Flush submission tasklet after bumping priority Chris Wilson
2018-05-07 13:57 ` [PATCH v2 2/7] drm/i915: Disable tasklet scheduling across initial scheduling Chris Wilson
2018-05-08 10:02 ` Tvrtko Ursulin
2018-05-08 10:31 ` Chris Wilson
2018-05-07 13:57 ` [PATCH v2 3/7] drm/i915/execlists: Make submission tasklet hardirq safe Chris Wilson
2018-05-08 10:10 ` Tvrtko Ursulin
2018-05-08 10:24 ` Chris Wilson
2018-05-08 10:56 ` Tvrtko Ursulin
2018-05-08 11:05 ` Chris Wilson
2018-05-08 11:38 ` Tvrtko Ursulin
2018-05-08 11:43 ` Chris Wilson
2018-05-08 17:38 ` Tvrtko Ursulin
2018-05-08 17:45 ` Tvrtko Ursulin
2018-05-08 20:59 ` Chris Wilson
2018-05-09 9:23 ` Chris Wilson
2018-05-07 13:57 ` [PATCH v2 4/7] drm/i915/guc: " Chris Wilson
2018-05-08 17:43 ` Tvrtko Ursulin
2018-05-07 13:57 ` [PATCH v2 5/7] drm/i915/execlists: Direct submit onto idle engines Chris Wilson
2018-05-08 10:23 ` Tvrtko Ursulin
2018-05-08 10:40 ` Chris Wilson
2018-05-08 11:00 ` Tvrtko Ursulin
2018-05-07 13:57 ` [PATCH v2 6/7] drm/i915/execlists: Direct submission from irq handler Chris Wilson
2018-05-08 10:54 ` Tvrtko Ursulin
2018-05-08 11:10 ` Chris Wilson
2018-05-08 11:53 ` Tvrtko Ursulin [this message]
2018-05-08 12:17 ` [PATCH] " Chris Wilson
2018-05-07 13:57 ` [PATCH v2 7/7] drm/i915: Speed up idle detection by kicking the tasklets Chris Wilson
2018-05-07 15:31 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/7] drm/i915: Flush submission tasklet after bumping priority Patchwork
2018-05-07 15:32 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-05-07 15:46 ` ✓ Fi.CI.BAT: success " Patchwork
2018-05-07 17:56 ` ✓ Fi.CI.IGT: " Patchwork
2018-05-08 9:40 ` [PATCH v2 1/7] " Tvrtko Ursulin
2018-05-08 9:45 ` Chris Wilson
2018-05-08 9:57 ` Tvrtko Ursulin
2018-05-08 14:11 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/7] drm/i915: Flush submission tasklet after bumping priority (rev2) Patchwork
2018-05-08 14:13 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-05-08 14:28 ` ✓ Fi.CI.BAT: success " Patchwork
2018-05-08 16:27 ` ✓ Fi.CI.IGT: " Patchwork
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