Re: [PATCH v2 1/9] drm/dp: Add definitions for POST_LT_ADJ training sequence

[Imre Deak <imre.deak@intel.com>]

On Thu, Feb 27, 2025 at 10:42:32PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Add the bit definitions needed for POST_LT_ADJ sequence.
> 
> v2: DP_POST_LT_ADJ_REQ_IN_PROGRESS is bit 1 not 5 (Jani)
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  include/drm/display/drm_dp.h | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
> index c413ef68f9a3..e2d2ae573d8b 100644
> --- a/include/drm/display/drm_dp.h
> +++ b/include/drm/display/drm_dp.h
> @@ -115,6 +115,7 @@
>  
>  #define DP_MAX_LANE_COUNT                   0x002
>  # define DP_MAX_LANE_COUNT_MASK		    0x1f
> +# define DP_POST_LT_ADJ_REQ_SUPPORTED	    (1 << 5) /* 1.3 */
>  # define DP_TPS3_SUPPORTED		    (1 << 6) /* 1.2 */
>  # define DP_ENHANCED_FRAME_CAP		    (1 << 7)
>  
> @@ -571,6 +572,7 @@
>  
>  #define DP_LANE_COUNT_SET	            0x101
>  # define DP_LANE_COUNT_MASK		    0x0f
> +# define DP_POST_LT_ADJ_REQ_GRANTED         (1 << 5) /* 1.3 */
>  # define DP_LANE_COUNT_ENHANCED_FRAME_EN    (1 << 7)
>  
>  #define DP_TRAINING_PATTERN_SET	            0x102
> @@ -788,6 +790,7 @@
>  
>  #define DP_LANE_ALIGN_STATUS_UPDATED                    0x204
>  #define  DP_INTERLANE_ALIGN_DONE                        (1 << 0)
> +#define  DP_POST_LT_ADJ_REQ_IN_PROGRESS                 (1 << 1) /* 1.3 */

DP2.1a also uses this flag as
"LANE_CNT_CONVERSION_FAILED" on UHBR, I guess that should be added
separately.

>  #define  DP_128B132B_DPRX_EQ_INTERLANE_ALIGN_DONE       (1 << 2) /* 2.0 E11 */
>  #define  DP_128B132B_DPRX_CDS_INTERLANE_ALIGN_DONE      (1 << 3) /* 2.0 E11 */
>  #define  DP_128B132B_LT_FAILED                          (1 << 4) /* 2.0 E11 */
> -- 
> 2.45.3
>