From: "Govindapillai, Vinod" <vinod.govindapillai@intel.com>
To: "intel-xe@lists.freedesktop.org" <intel-xe@lists.freedesktop.org>,
"Atwood, Matthew S" <matthew.s.atwood@intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Cc: "Roper, Matthew D" <matthew.d.roper@intel.com>
Subject: Re: [PATCH 02/10] drm/i915/xe3lpd: Adjust watermark calculations
Date: Wed, 9 Oct 2024 10:53:20 +0000 [thread overview]
Message-ID: <abc829fa09da7054ebd492747c41ba0c3766aad3.camel@intel.com> (raw)
In-Reply-To: <20241008223741.82790-3-matthew.s.atwood@intel.com>
On Tue, 2024-10-08 at 15:37 -0700, Matt Atwood wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
>
> Xe3 makes a couple minor tweaks to the watermark algorithm's block count
> calculations.
>
> Bspec: 68985
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> ---
> drivers/gpu/drm/i915/display/skl_watermark.c | 18 ++++++++++++------
> 1 file changed, 12 insertions(+), 6 deletions(-)
>
Looks good to me as per Bspec 68985
Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 6e1f04d5ef47..31de33e868df 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -718,7 +718,7 @@ static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
> int width, const struct drm_format_info *format,
> u64 modifier, unsigned int rotation,
> u32 plane_pixel_rate, struct skl_wm_params *wp,
> - int color_plane);
> + int color_plane, unsigned int pan_x);
>
> static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> struct intel_plane *plane,
> @@ -765,7 +765,7 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
> drm_format_info(DRM_FORMAT_ARGB8888),
> DRM_FORMAT_MOD_LINEAR,
> DRM_MODE_ROTATE_0,
> - crtc_state->pixel_rate, &wp, 0);
> + crtc_state->pixel_rate, &wp, 0, 0);
> drm_WARN_ON(&i915->drm, ret);
>
> for (level = 0; level < i915->display.wm.num_levels; level++) {
> @@ -1742,7 +1742,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
> int width, const struct drm_format_info *format,
> u64 modifier, unsigned int rotation,
> u32 plane_pixel_rate, struct skl_wm_params *wp,
> - int color_plane)
> + int color_plane, unsigned int pan_x)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> @@ -1803,7 +1803,9 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
> wp->y_min_scanlines,
> wp->dbuf_block_size);
>
> - if (DISPLAY_VER(i915) >= 10)
> + if (DISPLAY_VER(i915) >= 30)
> + interm_pbpl += (pan_x != 0);
> + else if (DISPLAY_VER(i915) >= 10)
> interm_pbpl++;
>
> wp->plane_blocks_per_line = div_fixed16(interm_pbpl,
> @@ -1845,7 +1847,8 @@ skl_compute_plane_wm_params(const struct intel_crtc_state *crtc_state,
> fb->format, fb->modifier,
> plane_state->hw.rotation,
> intel_plane_pixel_rate(crtc_state, plane_state),
> - wp, color_plane);
> + wp, color_plane,
> + plane_state->uapi.src.x1);
> }
>
> static bool skl_wm_has_lines(struct drm_i915_private *i915, int level)
> @@ -1909,7 +1912,10 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> }
> }
>
> - blocks = fixed16_to_u32_round_up(selected_result) + 1;
> + blocks = fixed16_to_u32_round_up(selected_result);
> + if (DISPLAY_VER(i915) < 30)
> + blocks++;
> +
> /*
> * Lets have blocks at minimum equivalent to plane_blocks_per_line
> * as there will be at minimum one line for lines configuration. This
next prev parent reply other threads:[~2024-10-09 10:53 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-08 22:37 [PATCH 00/10] Add xe3lpd edp enabling Matt Atwood
2024-10-08 22:37 ` [PATCH 01/10] drm/i915/xe3lpd: reuse xe2lpd definition Matt Atwood
2024-10-08 23:17 ` Matt Roper
2024-10-08 22:37 ` [PATCH 02/10] drm/i915/xe3lpd: Adjust watermark calculations Matt Atwood
2024-10-09 10:53 ` Govindapillai, Vinod [this message]
2024-10-08 22:37 ` [PATCH 03/10] drm/i915/xe3lpd: Add new display power wells Matt Atwood
2024-10-09 8:51 ` Luca Coelho
2024-10-08 22:37 ` [PATCH 04/10] drm/i915/xe3lpd: Update pmdemand programming Matt Atwood
2024-10-09 13:09 ` Govindapillai, Vinod
2024-10-09 13:53 ` Gustavo Sousa
2024-10-08 22:37 ` [PATCH 05/10] drm/i915/xe3lpd: Add cdclk changes Matt Atwood
2024-10-08 23:30 ` Matt Roper
2024-10-08 22:37 ` [PATCH 06/10] drm/i915/xe3lpd: Add macro to choose HDCP_LINE_REKEY bit Matt Atwood
2024-10-08 23:37 ` Matt Roper
2024-10-10 4:14 ` Kandpal, Suraj
2024-10-09 7:39 ` Jani Nikula
2024-10-10 4:17 ` Kandpal, Suraj
2024-10-10 8:09 ` Jani Nikula
2024-10-08 22:37 ` [PATCH 07/10] drm/i915/xe3lpd: Add C20 Phy consolidated programming table Matt Atwood
2024-10-09 20:32 ` Taylor, Clinton A
2024-10-08 22:37 ` [PATCH 08/10] drm/i915/xe3lpd: Add new bit range of MAX swing setup Matt Atwood
2024-10-09 6:13 ` Chauhan, Shekhar
2024-10-09 7:41 ` Jani Nikula
2024-10-08 22:37 ` [PATCH 09/10] drm/i915/xe3lpd: Add check to see if edp over type c is allowed Matt Atwood
2024-10-09 7:53 ` Jani Nikula
2024-10-09 23:06 ` Matt Atwood
2024-10-10 4:46 ` Kandpal, Suraj
2024-10-10 8:20 ` Jani Nikula
2024-10-08 22:37 ` [PATCH 10/10] drm/i915/xe3lpd: Add powerdown value of eDP over type c Matt Atwood
2024-10-09 5:57 ` Chauhan, Shekhar
2024-10-09 7:57 ` Jani Nikula
2024-10-09 23:05 ` Matt Atwood
2024-10-10 3:37 ` Kandpal, Suraj
2024-10-08 23:51 ` ✗ Fi.CI.CHECKPATCH: warning for Add xe3lpd edp enabling Patchwork
2024-10-08 23:51 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-10-08 23:59 ` ✓ Fi.CI.BAT: success " Patchwork
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