Re: [Intel-gfx] [PATCH 11/15] drm/i915/huc: track delayed HuC load with a fence

["Teres Alexis, Alan Previn" <alan.previn.teres.alexis@intel.com>]

Other than the one nit below, everything looks in order as per internal development and reviews...
but really wish we had the nit added - so we have a single location we can build on to get all
the various stages of gsc vs pxp vs huc operation sequences across hw gens (at least the first 
gen when it changes route).


Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com>



diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.h b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
> +enum intel_huc_delayed_load_status {
> +	INTEL_HUC_WAITING_ON_GSC = 0,
> +	INTEL_HUC_WAITING_ON_PXP,
> +	INTEL_HUC_DELAYED_LOAD_ERROR,
> +};
> +
>  struct intel_huc {
>  	/* Generic uC firmware management */
>  	struct intel_uc_fw fw;
> @@ -20,17 +28,28 @@ struct intel_huc {
>  		u32 mask;
>  		u32 value;
>  	} status;
> +
> +	struct {
> +		struct i915_sw_fence fence;
> +		struct hrtimer timer;
> +		struct notifier_block nb;
> +		enum intel_huc_delayed_load_status status;
> +	} delayed_load;
>  };


NIT: I really wish we had a state machine diagram for the huc load status
because of the prior, this and upcoming hw design progression - will be nice to
have a single place to look at the various flows (also for without
delayed-huc-loading case). Similiar to the diagram of what we have above
the definition of enum intel_uc_fw_status.