Re: [PATCH] drm/i915/display: Prevent DC6 while vblank is enabled for Panel Replay

["Hogander, Jouni" <jouni.hogander@intel.com>]

On Wed, 2024-09-11 at 17:23 +0300, Ville Syrjälä wrote:
> On Wed, Sep 11, 2024 at 01:14:33PM +0000, Hogander, Jouni wrote:
> > On Wed, 2024-09-11 at 16:00 +0300, Ville Syrjälä wrote:
> > > On Wed, Sep 11, 2024 at 03:40:15PM +0300, Jouni Högander wrote:
> > > > We need to block DC6 entry in case of Panel Replay as enabling
> > > > VBI
> > > > doesn't
> > > > prevent DC6 in case of Panel Replay.
> > > 
> > > This doesn't make sense to me. I *think* we are currently
> > > supposed to always operate in the "main link on" mode for panel
> > > replay.
> > 
> > This is not true. Check bspec 68920:
> > 
> > "When performing PR on an eDP port the Source will allow advanced
> > link
> > power management (ALPM) to turn the Main Link OFF when not sending
> > an
> > SDP or update region."
> 
> Right, it seems to be a thing for eDP only.
> 
> > 
> > And if you check block_dc6_needed in my patch that is checking eDP.
> > 
> > I was originally planning to handle this by preventing PR entry
> > when
> > VBLANK is enabled, but that would be more expensive from power
> > managements point of view -> decided to go with blocking DC6.
> 
> None of this explains how DC6 vs. DC5 is somehow different.
> DC5 should already turn of all the clocks/etc so nothing real
> can actually happen anymore. The only thing DC6 adds on top
> of DC5 is turning off some extra power wells.

Ok, based on your description I should use DC_STATE_DISABLE.

> 
> Hmm. So get_allowed_dc_mask() seems to be telling me that new
> platforms only have DC6 but no DC5. Is that correct or not?
> No idea. But that means we are in fact disabling all DC states
> and that at least explains how something might happen due to
> this patch.

Probably this is what happens. I will use DC_STATE_DISABLE instead.

> 
> The one thing that still doesn't quite make sense is that I would
> assume that the main link would get turned off regardless of DC6
> or not, which I would think causes the timing generator to stop
> anyway and should still give us no vblanks...

Comment from HW team was:

"Unlike PSR1/PSR2, the Transcoder’s timing generator never stops when
PR is Active (assuming DC6 is disabled), so the Transcoder will always
send V. Blank events to the interrupt structure."

BR,

Jouni Högander


>