Re: [PATCH 0/3] drm/i915/cx0: fix PLL enable failure handling on Meteor Lake

[Marco Nenciarini <mnencia@kcore.it>]

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Hi Aaron,

Short version: same regression reproduces on Arrow Lake-P with a
different NVIDIA SKU, and NVreg_EnableS0ixPowerManagement=1 is already
set on this machine. The S0ix knob alone is not sufficient to suppress
the race here, so the i915 side of the fix matters even on systems
where the NVIDIA workaround is in place.

Hardware:
  Dell Pro Max 16 Premium (MA16250)
  Intel Arrow Lake-P, Arc Pro 140T iGPU [8086:7d51]
  NVIDIA RTX PRO 1000 Blackwell [10de:2db8]
  NVIDIA driver 595.71.05 (open kernel modules)

Kernel: 7.0.4+deb13-amd64 (Debian 7.0.4-1~bpo13+1).

NVIDIA module options:
  NVreg_EnableS0ixPowerManagement=1
  NVreg_PreserveVideoMemoryAllocations=1
  NVreg_DynamicPowerManagement=0x00

Representative trace from a recent boot, ~45 minutes in, on the
internal eDP panel. The trigger was a VT switch out of the graphical
session via systemd-logind (vt_ioctl, fbcon_switch,
intel_fbdev_pan_display), not a direct s2idle resume; a suspend/resume
cycle had occurred earlier in the same boot:

  i915 0000:00:02.0: [drm] *ERROR* Failed to bring PHY A to idle.
  i915 0000:00:02.0: [drm] *ERROR* PHY A Read 0c70 failed after 3 retries.
  i915 0000:00:02.0: [drm] *ERROR* PHY A Write 0c70 failed after 3 retries.
  i915 0000:00:02.0: [drm] *ERROR* Timeout waiting for DDI BUF A to get active
  i915 0000:00:02.0: [drm] *ERROR* Timed out waiting for DP idle patterns
  i915 0000:00:02.0: [drm] *ERROR* [CRTC:149:pipe A] flip_done timed out
  i915 0000:00:02.0: [drm] *ERROR* [CRTC:149:pipe A] mismatch in port_clock
                                   (expected 540000, found 61440)
  WARNING ... intel_modeset_verify_crtc+0x325/0x550 [i915]
  WARNING ... verify_single_dpll_state+0x1a2/0x560 [i915]

After this point, every suspend/resume cycle in the same boot is
followed by [CONNECTOR:506:eDP-1] commit wait timed out, which is the
symptom your series is meant to make the driver fail cleanly on.

Happy to test the series on this hardware. Let me know whether you
prefer it tested against the current posting on drm-tip, or if a v2 is
in flight.

One small note: the cover-letter title says Meteor Lake, but the
cx0/C10 PHY path is shared with Arrow Lake-P (and Lunar Lake), so the
scope of the fix is wider than the title suggests. Worth widening in
v2 if you respin.

Thanks,
Marco

-- 
Marco Nenciarini - mnencia@kcore.it
7C23 B804 3E65 D298 0A21  B6E2 589F 03F0 1BA5 5038

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