Re: [PATCH v2 2/2] drm/i915/dsb: Use safe window path when VRR TG is used

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Mon, Jun 08, 2026 at 06:07:10PM +0530, Ankit Nautiyal wrote:
> When the VRR timing generator is always used, the hardware behaves
> as VRR-active regardless of crtc_state->vrr.enable.
> 
> The DSB paths that depend on the VRR safe window therefore need to follow
> the VRR code paths in that case too:
> - dsb_chicken(): program the SAFE_WINDOW chicken bits,
> - intel_dsb_vblank_evade(): use vmin/vmax vblank starts for the
>   wait window,
> - intel_dsb_wait_for_delayed_vblank(): wait inside the vmin safe window
>   before the scanline-based delayed vblank wait.
> 
> Introduce helper pre_commit_use_safe_window() and use it in the three sites
> 
> v2: Instead of modifying pre_commit_is_vrr_active() use a new helper and
> use it only in the required places. (Ville).
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dsb.c | 20 ++++++++++++++++----
>  1 file changed, 16 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
> index 07dd6318d9cc..d1441a86d1cc 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -210,6 +210,18 @@ static int dsb_scanline_to_hw(struct intel_atomic_state *state,
>  	return (scanline + vtotal - intel_crtc_scanline_offset(crtc_state)) % vtotal;
>  }
>  
> +static
> +bool pre_commit_use_safe_window(struct intel_atomic_state *state,
> +				struct intel_crtc *crtc)
> +{
> +	struct intel_display *display = to_intel_display(crtc->base.dev);
> +
> +	if (intel_vrr_always_use_vrr_tg(display))
> +		return true;
> +
> +	return pre_commit_is_vrr_active(state, crtc);
> +}
> +
>  /*
>   * Bspec suggests that we should always set DSB_SKIP_WAITS_EN. We have approach
>   * different from what is explained in Bspec on how flip is considered being
> @@ -229,7 +241,7 @@ static u32 dsb_chicken(struct intel_atomic_state *state,
>  	u32 chicken = intel_psr_use_trans_push(new_crtc_state) ?
>  		DSB_SKIP_WAITS_EN : 0;
>  
> -	if (pre_commit_is_vrr_active(state, crtc))
> +	if (pre_commit_use_safe_window(state, crtc))
>  		chicken |= DSB_CTRL_WAIT_SAFE_WINDOW |
>  			DSB_CTRL_NO_WAIT_VBLANK |
>  			DSB_INST_WAIT_SAFE_WINDOW |
> @@ -759,7 +771,7 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state,
>  	if (crtc_state->has_psr)
>  		intel_dsb_emit_wait_dsl(dsb, DSB_OPCODE_WAIT_DSL_OUT, 0, 0);
>  
> -	if (pre_commit_is_vrr_active(state, crtc) && crtc_state->vrr.dc_balance.enable) {
> +	if (pre_commit_use_safe_window(state, crtc) && crtc_state->vrr.dc_balance.enable) {

This one I think should keep using pre_commit_is_vrr_active().

>  		int vblank_delay = crtc_state->set_context_latency;
>  		int vmin_vblank_start, vmax_vblank_start;
>  
> @@ -788,7 +800,7 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state,
>  		end = vmax_vblank_start;
>  		start = end - vblank_delay - latency;
>  		intel_dsb_wait_scanline_out(state, dsb, start, end);
> -	} else if (pre_commit_is_vrr_active(state, crtc)) {
> +	} else if (pre_commit_use_safe_window(state, crtc)) {
>  		int vblank_delay = crtc_state->set_context_latency;
>  
>  		end = intel_vrr_vmin_vblank_start(crtc_state);

This will now emit two WAIT_DSL commands, which may be a bit confusing.
Might be better to add a completely separate branch to the if ladder
for this situation. And for consistency it should perhaps use
intel_mode_vblank_start() rather than intel_vrr_*_vblank_start()
since we're dealing with fixed refresh rate timings here.

> @@ -891,7 +903,7 @@ void intel_dsb_wait_for_delayed_vblank(struct intel_atomic_state *state,
>  		&crtc_state->hw.adjusted_mode;
>  	int wait_scanlines;
>  
> -	if (pre_commit_is_vrr_active(state, crtc)) {
> +	if (pre_commit_use_safe_window(state, crtc)) {
>  		/*
>  		 * If the push happened before the vmin decision boundary
>  		 * we don't know how far we are from the undelayed vblank.
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel