Re: [PATCH v3 2/3] drm/i915/fbc: Apply Wa_14028723391

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Tue, Oct 27, 2026 at 03:53:25PM +0000, Govindapillai, Vinod wrote:
> On Tue, 2026-10-27 at 17:13 +0200, Ville Syrjälä wrote:
> > On Tue, Oct 27, 2026 at 05:05:43PM +0200, Vinod Govindapillai wrote:
> > > Disable FBC in XE3P_LPD for FP16 formats with Alpha.
> > > 
> > > v2: Group the wa conditions as a separate function
> > >     Wa condition to check pixel blend mode
> > > 
> > > v3: use fomrat_is_float()
> > > 
> > > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> > > ---
> > >  .../gpu/drm/i915/display/intel_display_wa.c   |  2 ++
> > >  .../gpu/drm/i915/display/intel_display_wa.h   |  1 +
> > >  drivers/gpu/drm/i915/display/intel_fbc.c      | 22
> > > +++++++++++++++++++
> > >  3 files changed, 25 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c
> > > b/drivers/gpu/drm/i915/display/intel_display_wa.c
> > > index cc0b28d524f6..3df25104fb12 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_wa.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
> > > @@ -159,6 +159,8 @@ bool __intel_display_wa(struct intel_display
> > > *display, enum intel_display_wa wa,
> > >  		return IS_DISPLAY_VERx100(display, 1100, 1400);
> > >  	case INTEL_DISPLAY_WA_22021048059:
> > >  		return IS_DISPLAY_VER(display, 14, 35);
> > > +	case INTEL_DISPLAY_WA_14028723391:
> > > +		return DISPLAY_VER(display) == 35;
> > >  	default:
> > >  		drm_WARN(display->drm, 1, "Missing Wa: %s\n",
> > > name);
> > >  		break;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.h
> > > b/drivers/gpu/drm/i915/display/intel_display_wa.h
> > > index 2086c7da710d..5514771f513b 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_wa.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_wa.h
> > > @@ -56,6 +56,7 @@ enum intel_display_wa {
> > >  	INTEL_DISPLAY_WA_22012358565,
> > >  	INTEL_DISPLAY_WA_22014263786,
> > >  	INTEL_DISPLAY_WA_22021048059,
> > > +	INTEL_DISPLAY_WA_14028723391,
> > >  };
> > >  
> > >  bool __intel_display_wa(struct intel_display *display, enum
> > > intel_display_wa wa, const char *name);
> > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > index b84fa350c433..f70f3e34d655 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > @@ -1215,6 +1215,23 @@ static bool
> > > xe3p_lpd_fbc_pixel_format_is_valid(const struct intel_plane_state
> > > *p
> > >  	}
> > >  }
> > >  
> > > +static bool
> > > +intel_fbc_wa_14028723391_applies(const struct intel_plane_state
> > > *plane_state)
> > > +{
> > > +	struct intel_display *display =
> > > to_intel_display(plane_state);
> > > +	const struct drm_framebuffer *fb = plane_state->hw.fb;
> > > +
> > > +	/*
> > > +	 * Wa_14028723391:
> > > +	 * Fixes: Screen corruption with FBC enabled on a plane
> > > with the FP16
> > > +	 * Workaround: Disable FBC for FP16+Alpha in xe3p_lpd
> > > +	 */
> > > +	return intel_display_wa(display,
> > > INTEL_DISPLAY_WA_14028723391) &&
> > > +	       format_is_float(plane_state) &&
> > > +	       fb->format->has_alpha &&
> > > +	       plane_state->hw.pixel_blend_mode !=
> > > DRM_MODE_BLEND_PIXEL_NONE;
> > 
> > Seems overly complicated. Could just drop the alpha formats from
> > the list and be done with it.
> 
> This WA is "only" to NVL. This format supported from this platform
> onwards. So isn't this the right approach to list as supported though
> this WA counteract on that. 

The next platform can get its own pixel_format_is_valid() function.

> 
> Also gathered that, ARGB/ABGR with DRM_MODE_BLEND_PIXEL_NONE is treated
> like XRGB/XBGR. So aren't those case need to be allowed? And there is
> another existing case in the fbc_check_pane() where we do the same.

That is dead code. I also hope that userspace isn't dumb enough to
use a format with alpha needlessly.

-- 
Ville Syrjälä
Intel