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From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
	intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2 3/4] drm/i915: Setup PIPE_CHICKEN for fastsets too
Date: Tue, 5 Feb 2019 12:21:19 +0100	[thread overview]
Message-ID: <b09825b2-bb6f-568a-3a05-45f47345d43a@linux.intel.com> (raw)
In-Reply-To: <20190204202214.27051-1-ville.syrjala@linux.intel.com>

Op 04-02-2019 om 21:22 schreef Ville Syrjala:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Configure PIPE_CHICKEN during intel_update_pipe_config() to make
> sure we have our chickens in a row with fastboot too.
>
> v2: Apparently PIPE_CHICKEN is icl+ only
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 4087d54ea943..5b9b9791d290 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3958,6 +3958,9 @@ static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_sta
>  		I915_WRITE(SKL_BOTTOM_COLOR(crtc->pipe),
>  			   SKL_BOTTOM_COLOR_GAMMA_ENABLE |
>  			   SKL_BOTTOM_COLOR_CSC_ENABLE);
> +
> +	if (INTEL_GEN(dev_priv) >= 11)
> +		icl_set_pipe_chicken(crtc);
>  }
>  
>  static void intel_fdi_normal_train(struct intel_crtc *crtc)

Could we set it on the initial watermark sanitization pass somehow? In case userspace doesn't bother setting a mode?

During atomic check we test for distrust_bios_wm, but unfortunately it's cleared before the state is committed to hw.

Hmm there's intel_initial_commit, but that wouldn't work for the s4 resume path..

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  parent reply	other threads:[~2019-02-05 11:21 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-02-04 18:45 [PATCH 1/4] drm/i915: Fix wm latency==0 disable on skl+ Ville Syrjala
2019-02-04 18:45 ` [PATCH 2/4] drm/i915: Extract skl_set_pipe_chicken() Ville Syrjala
2019-02-04 20:21   ` [PATCH v2 2/4] drm/i915: Extract icl_set_pipe_chicken() Ville Syrjala
2019-02-04 23:28     ` Matt Roper
2019-02-04 18:45 ` [PATCH 3/4] drm/i915: Setup PIPE_CHICKEN for fastsets too Ville Syrjala
2019-02-04 20:22   ` [PATCH v2 " Ville Syrjala
2019-02-04 23:28     ` Matt Roper
2019-02-05 11:21     ` Maarten Lankhorst [this message]
2019-02-05 13:39       ` Ville Syrjälä
2019-02-05 14:49         ` Maarten Lankhorst
2019-02-05 18:30           ` Ville Syrjälä
2019-02-04 18:45 ` [PATCH 4/4] drm/i915: W/A for underruns with WM1+ disabled on icl Ville Syrjala
2019-02-04 20:22   ` [PATCH v2 " Ville Syrjala
2019-02-04 23:29     ` Matt Roper
2019-02-04 19:22 ` ✗ Fi.CI.BAT: failure for series starting with [1/4] drm/i915: Fix wm latency==0 disable on skl+ Patchwork
2019-02-04 21:08 ` ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Fix wm latency==0 disable on skl+ (rev4) Patchwork
2019-02-04 21:58 ` ✓ Fi.CI.IGT: " Patchwork
2019-02-04 23:07 ` [PATCH 1/4] drm/i915: Fix wm latency==0 disable on skl+ Matt Roper
2019-02-05 13:35   ` Ville Syrjälä
2019-02-05 13:42 ` [PATCH v2 " Ville Syrjala
2019-02-05 15:32   ` Matt Roper
2019-02-05 15:50 ` [PATCH v3 " Ville Syrjala
2019-02-05 16:46 ` ✓ Fi.CI.BAT: success for series starting with [v3,1/4] drm/i915: Fix wm latency==0 disable on skl+ (rev6) Patchwork
2019-02-05 19:47 ` ✓ Fi.CI.IGT: " Patchwork

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