From: Chris Wilson <chris@chris-wilson.co.uk>
To: Mika Kuoppala <mika.kuoppala@linux.intel.com>,
Damien Lespiau <damien.lespiau@gmail.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Fix sprite offset on HSW
Date: Fri, 26 Oct 2012 10:48:34 +0100 [thread overview]
Message-ID: <b94cdc$73kmsq@fmsmga001.fm.intel.com> (raw)
In-Reply-To: <873911hemr.fsf@gaia.fi.intel.com>
On Fri, 26 Oct 2012 10:33:00 +0300, Mika Kuoppala <mika.kuoppala@linux.intel.com> wrote:
> On Thu, 25 Oct 2012 17:10:01 +0100, Damien Lespiau <damien.lespiau@gmail.com> wrote:
> > @@ -127,13 +127,21 @@ ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
> >
> > I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
> > I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
> > - if (obj->tiling_mode != I915_TILING_NONE) {
> > - I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
> > +
> > + if (IS_HASWELL(dev)) {
> > + /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single
> > + * SPROFFSET register */
>
> I don't know if upper layers sanitize already but
> x should be < 8192 and y < 4096 in here, and both <4096 for ivb.
> Emit warning and clamp if they are not in range?
Should be -EINVAL on entry, and BUG_ON here if truly paranoid -
knowledge of the hardware is already spread across the layers.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
next prev parent reply other threads:[~2012-10-26 10:19 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-25 16:10 [PATCH] drm/i915: Fix sprite offset on HSW Damien Lespiau
2012-10-26 7:33 ` Mika Kuoppala
2012-10-26 9:48 ` Chris Wilson [this message]
2012-10-26 9:49 ` Daniel Vetter
2012-10-26 13:18 ` Paulo Zanoni
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